New Memory: DDR2-533, Continued
Basically DDR2 memory works similarly to DDR1 and operates with two data transfers per clock cycle (double data rate mode). However, DDR2 has been designed to reach much higher clock speeds. New features make an appearance here: On-die termination takes care of signal reflection, and reduced page sizes lower the energy required for activating pages. Posted CAS makes it possible to carry out a CAS command directly after the RAS signal without any collisions. This simplifies the design of the controller and increases the theoretical load that the memory can handle. At eight cycle bursts, the specification provides for a new burst type called Sequential Nibble, which divides the burst into two 4 bit Nibbles. Also, this enables burst lengths of eight cycles in interleaving mode.
The package type that memory manufacturers prefer will either be FBGA (fine-line ball grid array) or tiny BGA. As there is nothing new to tell in terms of performance, the following table should provide sufficient information.
|Memory Type||Clock Speed||Name||BandwidthSingle-Channel||BandwidthDual-Channel|
|DDR266||133 MHz DDR||PC2100||2,100 MB/s||4,200 MB/s|
|DDR333||166 MHz DDR||PC2700||2,700 MB/s||5,400 MB/s|
|DDR400||200 MHz DDR||PC3200||3,200 MB/s||6,400 MB/s|
|DDR2-400||200 MHz DDR||PC2 3200||3,200 MB/s||6,400 MB/s|
|DDR2-533||266 MHz DDR||PC2 4300||4,266 MB/s||8,533 MB/s|
|DDR2-667||333 MHz DDR||PC2 5300||5,333 MB/s||10,666 MB/s|
|DDR2-800||400 MHz DDR||PC2 6400||6,400 MB/s||12,800 MB/s|
Source: Micron DesignLine Vol. 12, 3Q03