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Intel Stakes Its Vision of the PC Future with 775 Launch

New Memory: DDR2-533, Continued

Basically DDR2 memory works similarly to DDR1 and operates with two data transfers per clock cycle (double data rate mode). However, DDR2 has been designed to reach much higher clock speeds. New features make an appearance here: On-die termination takes care of signal reflection, and reduced page sizes lower the energy required for activating pages. Posted CAS makes it possible to carry out a CAS command directly after the RAS signal without any collisions. This simplifies the design of the controller and increases the theoretical load that the memory can handle. At eight cycle bursts, the specification provides for a new burst type called Sequential Nibble, which divides the burst into two 4 bit Nibbles. Also, this enables burst lengths of eight cycles in interleaving mode.

The package type that memory manufacturers prefer will either be FBGA (fine-line ball grid array) or tiny BGA. As there is nothing new to tell in terms of performance, the following table should provide sufficient information.

Memory TypeClock SpeedNameBandwidthSingle-ChannelBandwidthDual-Channel
DDR266133 MHz DDRPC21002,100 MB/s4,200 MB/s
DDR333166 MHz DDRPC27002,700 MB/s5,400 MB/s
DDR400200 MHz DDRPC32003,200 MB/s6,400 MB/s
DDR2-400200 MHz DDRPC2 32003,200 MB/s6,400 MB/s
DDR2-533266 MHz DDRPC2 43004,266 MB/s8,533 MB/s
DDR2-667333 MHz DDRPC2 53005,333 MB/s10,666 MB/s
DDR2-800400 MHz DDRPC2 64006,400 MB/s12,800 MB/s

Source: Micron DesignLine Vol. 12, 3Q03