New Interlink: PCI Express
Three x1 and one x16 PCI Express slots.
Different from PCI or PCI-X, PCI Express (or PCIe) is based on a serial protocol. This means that the interface can get by with a very limited number of wires. In exchange, these are clocked much faster than the PCI bus in order to obtain a high bandwidth. Additionally, that bandwidth can be easily multiplied by merging several PCI Express lanes. The specification provides for five different slot types: x16, x8, x4, x2 and x1, whereas that is referred to as "by sixteen", taking the widest PCIe variant as an example.
PCI Express is a bi-directional point-to-point link, meaning that it basically offers the same bandwidth in both directions and does not need to share its bandwidth with other devices, as is the case with parallel PCI. Due to its modular architecture, motherboard makers will be able to distribute the available PCI Express resources to their preferred slot configuration. A total of 20 PCI Express lanes can be arranged as one x16 PCIe slot and four x1 PCIe slots, which is also common practice with the 900 chipset series. Or five x4 PCIe ports can be implemented for mid-range server systems. Whatever is mathematically doable can be implemented with PCI Express. Also, PCI Express could make it possible to mix chipset components from different manufacturers.
Both the PCI bus and AGP are to be replaced by PCI express. Although Intel does not support AGP with any of the new chipsets, we expect the interface to remain in the market for approximately one more year. It might even take much longer until the PCI bus disappears, but because the costs for implementing this interface are quite low today, that should never be a problem.
|PCI Express Lines||Bandwidth per Stream||Bandwidth, duplex|
|1||256 MB/s||512 MB/s|
|2||512 MB/s||1 GB/s|
|4||1 GB/s||2 GB/s|
|8||2 GB/s||4 GB/s|
|16||4 GB/s||8 GB/s|
|32*||8 GB/s||16 GB/s|