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South Korea unveils $520 billion investment plan with Samsung and SK Hynix to expand memory chip dominance
President Lee unveiled an 800 trillion won ($520B) public-private plan for four new Samsung and SK Hynix fabs, dwarfing the US CHIPS Act tenfold.
Imec's 2026 roadmap details 0.3nm nodes by 2038, CFET transistors become viable at 0.7nm
Premium As CPP shrinking stalls, chipmakers find a new way to increase transistor density. Imec foresees 0.3nm in 2038, CFET insertion in 2038, HLSI era.
IBM goes sub-1nm, develops 0.7nm-class technology
IBM's new 0.7nm-class fabrication process uses nanostack transistors, requires 2x more FEOL steps for massive improvements in performance, power, and area.
TSMC is reportedly hiking prices for 'all advanced nodes,' accounting for 74% of the company’s wafer business
TSMC has reportedly told customers to prepare for 5% to 10% price hikes across advanced chip nodes, extending beyond 3nm to include 7nm and some legacy processes.
Rare ASML Special Edition Monopoly board unearthed in social media trade
We just witnessed a significant semiconductor industry related non-cash trade deal take place on Twitter/X.
ASML denies US government report that its EUV chipmaking tool was shipped to China
U.S. Commerce Secretary Lutnick expresses concerns in a conversation with ASML executives that China has an EUV lithography system as ASML denies shipping such scanners to the PRC.
Post-silicon era gets closer as industry giants crack the 2D transistor scaling bottleneck with breakthrough tech
Imec, ASML, and TSMC have integrated both n-type and p-type transistors with atomically thin 2D channels on a single 300mm wafer.
Intel's fab roadmap examined — Arizona, Ohio, Ireland, and the two deadlines deciding 14A process node
Premium This roadmap provides an in-depth analysis of Intel's current plans for its chip production capacity.
