RISC V: The Open Standard Architecture
Latest about RISC V
First RISC-V 3D GPUs Will Be Demoed Next Week
By Mark Tyson published
Claimed to be the industry's first RISC-V 3D GPUs for graphics and deep learning tasks.
Researchers Benchmark Experimental RISC-V Supercomputer
By Anton Shilov published
Italian students experiment with an eight-node 32-core RISC-V supercomputer.
Chinese Loongson Claims Next-Gen CPU Matches AMD's Zen 3
By Anton Shilov published
Loongson expects its next-generation microarchitecture to match Zen 3's IPC.
Loongson Gearing Up to Ship 16-Core CPUs
By Anton Shilov published
Loongson’s 16-core processors based on LoongArch are heading to servers.
Intel to Explore RISC-V Architecture for Zettascale Supercomputers
By Anton Shilov published
Intel and Barcelona Supercomputing Center to invest €400 million in laboratory developing RISC-V CPUs for supercomputers.
GCC Gains Loongson's LoongArch Architecture Support
By Anton Shilov published
GNU Compiler Collection now supports Chinese LoongArch instruction set architecture.
China's Ubuntu Kylin Targets Second RISC-V Board
By Ian Evenden published
China and Canonical's joint project reaches version 22.04 LTS, and seeks new home
Startup Plans Nuclear-Powered Data Centers on the Moon
By Anton Shilov published
The moon can be an ideal place for datacenters in the distance future: easy cooling, loads of power, but still very expensive.
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