MIPS Introduces Code Compression Chips
Fitting 32-bit code into 16-bit space.
We often hear lots about the latest desktop and notebook processors, but rarely do we go into detail about the chips that power the smaller devices in our cars, set top boxes, routers, etc.
Today MIPS Technologies introduced a new core family comprised of the MIPS32 M14K and M14Kc cores, which are the first MIPS32-compatible cores that also execute the new microMIPS instruction set architecture (ISA), enabling performance of 1.5 DMIPS/MHz with an advanced level of code compression.
The new microMIPS ISA maintains 98 percent of MIPS32 performance while reducing code size by 35 percent, or in other words, it gives 32-bit performance with near 16-bit code sizes. This translates to significant silicon cost savings, which could be passed onto the consumer.
"Growing amounts of signal processing and higher speed connectivity are driving up the performance requirements in MCUs and many cost-sensitive embedded applications, while still requiring a very small silicon footprint," said Art Swift, vice president of marketing at MIPS Technologies. "We’re enabling our customers to develop high-performance devices in smaller form factors to significantly decrease development costs. We’re pleased to enhance and expand our offering for MCU and system designers with these groundbreaking new cores."
Besides its use in microcontrollers, the M14K micro-architecture supports a Linux and Java engine, making it viable for implementation inside an Android platform with its full cache controller and translation lookaside buffer (TLB) memory management unit (MMU).
System designers will be able to integrate the new M14K and M14Kc cores in the first quarter of 2010.