DDR3-1333 Speed and Latency Shootout

OCZ PC3-10666 ReaperX HPC Enhanced Bandwidth

Anyone impressed by the fact that OCZ's medium-performance Platinum Edition is rated at the same timings of some competitor's high-end parts will be even more impressed by the rated timings of its ReaperX series. Equipped with a twin-heatpipe radiator, each ReaperX module is rated for a 1333 MHz data rate at CAS 6.

But while CAS 6 might sound impressive, these are no ordinary CAS 6 timings. The full set of standard timings is 6-5-5-18, which is quicker than the 6-6-6-x timings normally associated with the "CAS 6" label. The elaborate cooling system comes into play here, as the recommended setting to reach 6-5-5-18 timings at DDR3-1333 is 1.85 volts.

So the builder must enter BIOS and manually configure the speed, latency and voltage in order to run ReaperX modules at rated performance levels. This is excusable for a module set that's marketed towards the "extreme performance" crowd who should be familiar with BIOS configuration, but might seem a bit daunting to new builders.

In fact, even at its 533 MHz SPD value (DDR3-1066), these part number OCZ3RPX1333EB2GK ReaperX modules use 6-5-5-20 rather than 6-5-5-18 timings, but at least the DDR3-1066 automatic configuration is provided to ease "first boot" stability prior to any manual BIOS changes.

Missing is any DDR3-1333 SPD value, and we instead find an odd DDR3-1244 value of 622 MHz clock speed and a DDR3-1422 value of 711 MHz. None of our boards defaulted to DDR3-1422 timings at DDR3-1333 clock speeds when using an FSB-1333 processor, but instead the ReaperX modules always dropped to DDR2-1066 via automatic configuration. CPU-Z indicates that this may be because the modules are electronically labeled as PC3-8500 rather than PC3-10700.

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  • dv8silencer
    I have a question: on your page 3 where you discuss the memory myth you do some calculations:


    "Because cycle time is the inverse of clock speed (1/2 of DDR data rates), the DDR-333 reference clock cycled every six nanoseconds, DDR2-667 every three nanoseconds and DDR3-1333 every 1.5 nanoseconds. Latency is measured in clock cycles, and two 6ns cycles occur in the same time as four 3ns cycles or eight 1.5ns cycles. If you still have your doubts, do the math!"

    Based off of the cycle-based latencies of the DDR-333 (CAS 2), DDR2-667 (CAS 4), and DDR3-1333 (CAS8), and their frequences, you come to the conclusion that each of the memory types will retrieve memory in the same amount of time. The higher CAS's are offset by the frequences of the higher technologies so that even though the DDR2 and DDR3 take more cycles, they also go through more cycles per unit time than DDR. How is it then, that DDR2 and DDR3 technologies are "better" and provide more bandwidth if they provide data in the same amount of time? I do not know much about the technical details of how RAM works, and I have always had this question in mind.
    Thanks
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  • Anonymous
    Latency = How fast you can get to the "goodies"
    Bandwidth = Rate at which you can get the "goodies"
    1
  • Anonymous
    So, I have OCZ memory I can run stable at
    7-7-6-24-2t at 1333Mhz or
    9-9-9-24-2t at 1600Mhz
    This is FSB at 1600Mhz unlinked. Is there a method to calculate the best setting without running hours of benchmarks?
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  • Anonymous
    Sorry dude but you are underestimating the ReapearX modules,
    however hard I want to see what temperatures were other modules at
    a voltage of ~ 2.1v, does not mean that the platinum series is not performant but I saw a ReapearX which tended easy to 1.9v(EVP)940Mhz, that means nearly a DDR 1900, which is something, but in chapter of stability/temperature in hours of functioning, ReapearX beats them all.
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  • Anonymous
    All SDRAM (including DDR variants) works more or less the same, they are divided in banks, banks are divided in rows, and rows contain the data (as columns).
    First you issue a command to open a row (this is your latency), then in a row you can access any data you want at the rate of 1 datum per cycle with latency depending on pipelining.

    So for instance if you want to read 1 datum at address 0 it will take your CAS lat + 1 cycle.

    So for instance if you want to read 8 datums at address 0 it will take your CAS lat + 8 cycle.

    Since CPUs like to fill their cache lines with the next data that will probably be accessed they always read more than what you wanted anyway, so the extra throughput provided by higher clock speed helps.

    But if the CPU stalls waiting for RAM it is the latency that matters.
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  • Anonymous
    what is on pc3-10600s "s" ?
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