DDR3-1333 Speed and Latency Shootout

By Thomas Soderstrom
published

Test Settings: Lowest Stable Latencies, Continued

Though hard drive performance isn't expected to improve the scores of our chosen benchmarks, using a 10,000 RPM part certainly won't hurt these. Western Digital's ancient 150 GB Raptor remains the top part.

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Latency Test Benchmarks and Settings
3D-Games
F.E.A.RVersion: 1.0 RetailVideo Mode: 1024x768Computer: MediumGraphics: MediumTest Path: Options/Performance/Test Settings
Quake 4Version: 1.2 (Dual-Core Patch)Video Mode: 1024x768Video Quality: defaultTHG Timedemo waste.maptimedemo demo8.demo 1 (1 = load textures)
Audio
Lame MP3Version 3.97 Beta 2 (12-22-2005)Audio CD "Terminator II SE", 53 minwave to mp3160 kbps
OGGVersion 1.1.2 (Intel P4 MOD)Version 1.1.2 (Intel AMD MOD)Audio CD "Terminator II SE", 53 minwave to oggQuality: 5
Video
TMPEG 3.0 ExpressVersion: 3.0.4.24 (no Audio)fist 5 Minutes DVD Terminator 2 SE (704x576) 16:9Multithreading by rendering
DivX 6.6Version: 6.6Profile: High Definition Profile1-pass, 3000 kb/sEncoding mode: Insane QualityEnhanced multithreadingno Audio
XviD 1.1.3Version: 1.1.3Target quantizer: 1.00
Applications
Autodesk 3D Studio MaxVersion: 8.0Characters "Dragon_Charater_rig"rendering HTDV 1920x1080
Synthetics
PCMark05 ProVersion: 1.1.0Memory TestsWindows Media Player 10.00.00.3646Windows Media Encoder 9.00.00.2980
SiSoftware Sandra 2005Version 2005.7.10.60Memory Test = Bandwidth Benchmark
Thomas Soderstrom
Thomas Soderstrom
Thomas Soderstrom is a Senior Staff Editor at Tom's Hardware US. He tests and reviews cases, cooling, memory and motherboards.
6 Comments Comment from the forums
  • dv8silencer
    I have a question: on your page 3 where you discuss the memory myth you do some calculations:


    "Because cycle time is the inverse of clock speed (1/2 of DDR data rates), the DDR-333 reference clock cycled every six nanoseconds, DDR2-667 every three nanoseconds and DDR3-1333 every 1.5 nanoseconds. Latency is measured in clock cycles, and two 6ns cycles occur in the same time as four 3ns cycles or eight 1.5ns cycles. If you still have your doubts, do the math!"

    Based off of the cycle-based latencies of the DDR-333 (CAS 2), DDR2-667 (CAS 4), and DDR3-1333 (CAS8), and their frequences, you come to the conclusion that each of the memory types will retrieve memory in the same amount of time. The higher CAS's are offset by the frequences of the higher technologies so that even though the DDR2 and DDR3 take more cycles, they also go through more cycles per unit time than DDR. How is it then, that DDR2 and DDR3 technologies are "better" and provide more bandwidth if they provide data in the same amount of time? I do not know much about the technical details of how RAM works, and I have always had this question in mind.
    Thanks
    Reply
  • Latency = How fast you can get to the "goodies"
    Bandwidth = Rate at which you can get the "goodies"
    Reply
  • So, I have OCZ memory I can run stable at
    7-7-6-24-2t at 1333Mhz or
    9-9-9-24-2t at 1600Mhz
    This is FSB at 1600Mhz unlinked. Is there a method to calculate the best setting without running hours of benchmarks?
    Reply
  • Sorry dude but you are underestimating the ReapearX modules,
    however hard I want to see what temperatures were other modules at
    a voltage of ~ 2.1v, does not mean that the platinum series is not performant but I saw a ReapearX which tended easy to 1.9v(EVP)940Mhz, that means nearly a DDR 1900, which is something, but in chapter of stability/temperature in hours of functioning, ReapearX beats them all.
    Reply
  • All SDRAM (including DDR variants) works more or less the same, they are divided in banks, banks are divided in rows, and rows contain the data (as columns).
    First you issue a command to open a row (this is your latency), then in a row you can access any data you want at the rate of 1 datum per cycle with latency depending on pipelining.

    So for instance if you want to read 1 datum at address 0 it will take your CAS lat + 1 cycle.

    So for instance if you want to read 8 datums at address 0 it will take your CAS lat + 8 cycle.

    Since CPUs like to fill their cache lines with the next data that will probably be accessed they always read more than what you wanted anyway, so the extra throughput provided by higher clock speed helps.

    But if the CPU stalls waiting for RAM it is the latency that matters.
    Reply
  • what is on pc3-10600s "s" ?
    Reply