Architecture Diagram Of The Celeron Willamette
Some of you might remember this diagram, which dates back to the end of 2000 when the Pentium 4 was first introduced. It's still valid today - nothing has changed, except the fact that the processor we are talking about is called Celeron rather than Pentium 4.
Please see the initial Pentium 4 review for more details on the Willamette core.
Celeron: A Little History
The first Celeron was a Slot-1 model which was based on the Pentium II Deschutes (0.25 µm, 266 MHz) - but it had to live without an L2 cache. Only its successor called Mendocino was equipped with 128 kB L2 cache on-chip. The Celeron Mendocino was available at 300 and 333 MHz.
The next generation Celeron moved to Socket 370 and remained with the Mendocino core, but in contrast to the Pentium III, Celeron had to live with only 128 kB cache again, and slower FSB speed as well. In exchange, the cache was on-die again. This processor also performed the transition from Slot-1 to Socket 370 . Since then, the Celeron has been known for being an inexpensive and very overclockable CPU, letting overclockers achieve clock speeds of up to 50% above specs. For example, a Celeron 300 MHz could be overclocked to 450 MHz (by running the FSB at 100 rather than at 66 MHz). Versions at 333, 366, 400, 466, 500 and 533 MHz were available. In contrast to the Pentium III Katmai, the Celerons had to live with only 66 MHz instead of 100 MHz FSB.
Next, the Celeron Coppermine followed. The die became much smaller, thus the Pentium III processors were equipped with 256 kB cache. In addition, the transition to 133 MHz FSB was made. Again, the Celeron had to stay at 66 MHz for a long time. It was available with various clock speeds: 533, 566, 600, 633, 667, 700, 733 and 766 MHz. At 800 MHz and above, the Celeron Coppermine was finally allowed to run 100 MHz FSB. It was available at clock speeds of 800, 850, 900, 950, 1000 and 1100 MHz.
Last but not least, there is the Celeron Tualatin - based on the most recent version of the Pentium III core. Finally, it was given a 256 kB L2 cache , since the Pentium III had been upgraded to 512 kB optionally.
