Mobile Dual Core Processors
From a technology standpoint, the Core Duo / Core 2 Duo and the Turion 64 X2 are not far away from their desktop brothers, which are the Core 2 Duo by Intel and the Athlon 64 X2 by AMD. Both processor families use the same microarchitecture and thus offer very much the same feature sets.
Intel's advantage is its mature 65 nm manufacturing process, which allows the company to install as much as 4 MB of L2 cache onto a mobile processor. As you can see in the table below, the Core 2 Duo processor has a smaller die size than the Turion 64 X2 - 143 mm² compared to 183 mm² - despite having four times the L2 cache capacity. However, all AMD64 processors come with an integrated dual channel memory controller and a crossbar switch for inter-core communication, which requires silicon real estate. The memory support for Core 2 Duo notebooks relies on the platform core logic, which typically is a 945M/GM chipset today. It offers a dual channel DDR2-667 memory interface as well.
Both processors require a maximum of 30-35 W when running under full load, and both will throttle the core clock speed and operating voltage when they run idle. AMD calls this PowerNow!, while Intel refers to Enhanced SpeedStep Technology; essentially, the mechanisms are very much the same.
Intel offers low-voltage versions of its Core 2 Duo (L7200, L7400), which require only 17 W. An ultra-low voltage version for ultra mobile solutions and special applications, requiring only 9 W at 1.06 GHz, is expected soon as well.
| Header Cell - Column 0 | AMD Turion 64 X2 | Intel Core 2 Duo |
|---|---|---|
| Code Name | Taylor, Trinidad | Merom |
| Architecture | AMD64 | Core |
| Socket | S1, 638 pins | 479 |
| Interface | HyperTransport (HT800) | AGTL+ Bus (FSB533, FSB800) |
| Manufacturing | 90 nm SOI | 65 nm |
| Memory Controller | Dual Channel DDR2-667 | n/a (part of the platform core logic) |
| Processing Cores | 2 | 2 |
| L1 Cache | 64 kB Data, 64 kB Instruction Cache per Core | 32 kB Data, 32 kB Instruction Cache per Core |
| L2 Cache | 512 kB per Core | 2 MB or 4 MB unified for both Cores |
| Clock Speeds | 1.6 - 2.0 GHz | 1.6 - 2.33 GHz |
| Die Size | 183 mm² | 111/143 mm² (2/4 MB L2 Cache) |
| Transistor Count | 154 million | 167/291 million (2/4 MB L2 Cache) |
| Operating Voltage Range | 0.8 - 1.1 V | 1.0375 - 1.30 V |
| Thermal Design Power (TDP) | 31, 33, 35 W | 34 W |
| Power Saving Features | PowerNow! | Sleep Transistors, Enhanced SpeedStep |
| Instruction Set Enhancements | MMX, E3DNow!, SSE, SSE2, SSE3, NX-Bit, Pacifica VT | MMX, SSE, SSE2, SSE3, SSSE3, EM64T, XD-Bit, iVT (4 MB L2 Cache only) |
