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More details emerge about how Intel now earns more revenue from each wafer by looking to the edges — analyst reports say reduced yield variability across each wafer leads to more sellable CPUs
One of the highlights of Intel's first-quarter earnings report last week was improved sales of its client and data center processors as a result of improved output and yield, as well as high demand. Last week, industry analyst Ben Bajarin said the company was now selling what would normally be 'scrap' or 'low-expectation' CPUs, which helped boost margins. We followed up with industry veteran Dan Hutcheson for more details, and he notes that some of the company's recent yield gains are less about breakthrough inventions and more about disciplined execution improvements under its new manufacturing leadership.
Dan Hutcheson, vice chair of TechInsights, told Tom's Hardware that while techniques like binning and statistical process control (SPC) have been standard practice at Intel for about 40 years, recently — starting from around late 2024 when Naga Chandrasekaran, the current head of Intel Foundry, joined the company — Intel focused on tightening yield distribution across the wafer by reducing edge-related variability.
Specifically, Intel now runs a continuous process improvement (CPI) program after a node enters high-volume manufacturing, so by now it has implemented certain edge-specific process correction methods in a bid to reduce quality variability from the center to the edge of a wafer to get more sellable silicon from a single wafer.
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"When it comes to manufacturing, it takes a year or two to make these kind of dramatic changes," Hutcheson told Tom's Hardware. "There’s just nothing new here. Intel has binned lots since the 1980s. Yield distributions are always heteroscedastic from the center to the edge of the wafer. Actually, one of the things Naga Chandrasekaran's yield management efforts have changed is to narrow the spread to the edge of the wafer. Hence, they are getting more revenue-per-wafer for little cost. The beauty of it is that the improvements are node independent."
As a result, Intel can now extract more high-quality dies from a single wafer and, perhaps even more importantly, more sellable dies from a single wafer, which improves output and productivity. Essentially, chips that previously might have been scrapped or too marginal to sell are now binned into lower-tier SKUs and sold because the demand is strong, according to Ben Bajarin, chief executive and principal analyst at Creative Strategies.
"Got some clarity from Intel IR on additional lift to margins," Bajarin wrote in an X post. "Intel got an unexpected margin lift from better yield salvage. Chips that would normally have been lower-value edge-die on the wafer were binned down and still sold into usable SKUs, turning what may have been scrap or low-expectation output into incremental revenue. Customers did not care, just said 'I will take it all.' That is the demand environment we are in for CPUs."
This can be interpreted in different ways, but it is feasible that the yield distribution improvements have made lower-quality chips now viable products, or that the company created even lower-tier SKUs to harvest even more chips.
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More importantly, the aforementioned tightening yield distribution improvements are said to be largely node-independent, which means they benefit multiple process technologies rather than the existing nodes, such as Intel 7/4/3. Indeed, there are many ways to reduce edge-related variability, and many of them are node independent, which means some of the methods developed at Intel should be applicable to 18A (though that isn't confirmed). In fact, one of the comments Intel made during its earnings call is that the yield curve of 18A progresses at a pace that is higher than expected.
"Lip-Bu had a [18A yield] target as we came into this year for the end of this year, and we are probably going to hit that probably the middle of this year," said David Zinsner, chief financial officer of Intel. "So, you know, he has done a very good job working the team to drive a better response there."
Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.
When I first read "edge", I thought they meant better utilisation for packing rectangular chips on a circular wafer, so that the edges of the wafer aren't wasted.
Or is there a specific reason why chips have to be laid out in grids?
When I first read "edge", I thought they meant better utilisation for packing rectangular chips on a circular wafer, so that the edges of the wafer aren't wasted.
Or is there a specific reason why chips have to be laid out in grids?
In order to scribe and break a wafer into individual die, the wafer is laid out with common scribelanes in both directions. The scribe saw cuts across entire wafer in a straight line: but not through the entire wafer. To finish the cut, the wafer is gently shook to break it up
So in effect, the wafer looks like straight roads that define rectangular "city blocks".
The edge will lose die for several reasons: partial/incomplete die images, variable processing, etc.
Any good processing will try to "center" and tighten the process window to optimize yields: this helps improve an entire wafer's yield as well improve performance. I'm shocked Intel had lost this basic silicon mfg discipline.
I'm shocked Intel had lost this basic silicon mfg discipline.
I was going to say this makes it sound like they weren't bothering to try to improve yields past a certain point until they got desperate. I suppose efforts to do that had diminishing returns until the possibility of higher profits came into play, but they really make it sound like the new guy is doing something revolutionary by even trying, not just implementing new methods to go further.
I was going to say this makes it sound like they weren't bothering to try to improve yields past a certain point until they got desperate.
Desperate for what?!?
This is about demand being so high that it makes this profitable, and/or ,this is about customers being so desperate that they buy anything.
This article is still not at all clear about which one is happening.
Intel doesn't need to be desperate to want to maximize profits, that's what they always try to do.
Actually the better they do the better their ability to maximize profits.
When I first read "edge", I thought they meant better utilisation for packing rectangular chips on a circular wafer, so that the edges of the wafer aren't wasted.
I have often thought about this, why can’t the manufacturers make other smaller chips at the edges of the wafer so as to use more of the silicon?
I have often thought about this, why can’t the manufacturers make other smaller chips at the edges of the wafer so as to use more of the silicon?
A lot has changed since i worked in intel's fab11 from 1995-2000 we used an 8" wafer and made pentiums. Just guessing , but it may come down to the reticle in photolithography They are expensive and at the time contained about 4 dies at a time. If you added the extra chip on the die, it would be throughout the wafer, not just the edge. Im guessing, But it may be why. Plus there's a certain amount of steps (some over 300) that determine what gets applied, or removed at each step. Highly unlikely its the same for 2 different chips.
I mean, other than people wanting to overclock (or run highest boost all core boost clock if they're not actually overclocking), I think a lot of people would have been perfectly happy to buy low bin chips. Nice that they've stopped just throwing them out.
