The Hypertransport Technology Consortium today released the third generation of the Hypertransport chip-to-chip interconnect. The new version 3.0 increases the total available bandwidth from 22.4 GB/s in version 2.0 to 41.6 GB/s. The initial specification released in 2001 provided Hypertransport 1.0 with a bandwidth of 12.8 GB/s. The 1.4 GHz dual data rate (DDR) maximum clock of HyperTransport 2.0 is extended to up to 2.6 GHz in version 3.0
According to the Hypertransport Consortium, is "fully backwards-compatible" with earlier versions of the HyperTransport specification standard.
Besides more bandwidth, the new spec also delivers an AC interconnect to complement the existing DC mode, which allows to increase Hypertransport's maximum signal transmission distance to 1 meter (about 3 ft) at maximum specified clock speed with no signal transmission or performance degradation, according to the consortium. As a result, the technology can now support "long-haul signal transmission typical of backplane and chassis-to-chassis applications," the consortium said.
The spec also includes hot plugging to add or remove Hypertransport device to an from a system, a power-management mode with self-configuring power management capabilities and an optional "un-ganging mode" which enables a 1x16 Hypertransport link to be configured as 2x8 virtual links.