DDR3 Memory Basics
DDR3 memory is technically very similar to DDR2. It also supports termination, but it is based on each die rather than on the motherboard. Optional temperature probes allow adjusting termination to the actual environmental conditions. The most important difference can be found inside the memory itself, which is now specified to run at 1.5 V instead of 1.8 V.
While DDR3 memory is still based on a base clock speed of up to 200 MHz and double data rate technology - which transfers data on the raising and falling edges of the clock signal - the DDR3 prefetch has been widened to eight bits. This results in a doubled interface clock speed compared to DDR2 (four bits prefetch) and a quadrupled performance when compared to DDR1 (two bit prefetch). Hence the speeds are rated DDR3-800 to DDR3-1600, although the memory clock speed at DDR3-1600 is still 200 MHz.
Additional silicon real estate is needed for the circuitry for the 8-bit prefetch, read/write amplifiers, on-die termination, and fly-by architecture to address memory via the DQS (data queue strobe). This means that 1 Gbit and especially 512 Mbit DDR3 chips are not very efficient from a capacity per die size standpoint. At this point, Qimonda has been shipping 512 Mbit DDR3 on its 75 nm process. Samsung Semiconductor has produced 1 Gbit DDR3 SDRAMs using its 80 nm process, while it is switching to a 68 nm process. Micron has already been working on a 78 nm process, shipping 2 Gbit DDR3 parts. Hynix is also about to move to a 66 nm process for 2 Gbit components. You get the point: reducing the feature size allows the memory companies to offer higher capacity chips that also save some power thanks to the voltage reduction, while enabling new margins for faster clock speeds. Hence DDR3 will not have its breakthrough before 2 GB DDR3 parts become mainstream, which will enable 2 GB DDR2 modules to be made for an acceptable cost.
Both DDR2 and DDR3 DIMMs have 240 pins, but the notch was relocated to avoid confusing DDR2 and DDR3. Apart from that, the transition from DDR2 to DDR3 is relatively simple when looking at matters from the controller side. The increased prefetch is the main reason for the higher latency that can be observed across various DDR3 memory modules. We were used to 2, 2.5 or 3 clock cycles for column access (CAS latency) with DDR1, and 3 to 5 clocks for DDR2. DDR3 requires at least 5 clock cycles for the same procedure, due to the more complex 8-bit prefetch circuitry. While certain timing cycles do in fact require more time, the increased clock speeds cushion the potentially negative impact of longer latencies. As long as clock speeds double together with the latencies, e.g. DDR2-800 at CL4 vs. DDR3-1600 at CL8, nothing really changes.
The performance benefit of switching from one memory generation to the next has never been spectacular, although the theoretical bandwidth has increased a lot. PC3200 memory (DDR400) has a gross throughput of 3.2 GB/s, DDR2-800 is called PC2-6400, equaling 6.4 GB/s, and DDR3-1600 equals PC3-12800 or 12.8 GB/s. Since desktop PCs typically run memory in two channels, the effective gross bandwidth is twice as high: 6.4 GB/s for dual channel DDR400, 12.8 GB/s for DDR2-800 and 25.6 GB/s for DDR3-1600 in two channels. Larger processor caches allow the transfer of more and more code directly into the processor, so fast memory is not as important as it used to be.