Besides the processor designs that have already been announced there will be two additional versions. The desktop processor Allendale is a stripped-down dual core with 2 MB L2 cache only. We expect this processor to be available a couple of months after Conroe.
Later on, Intel is going to release even more Merom-based products, yet stripped-down again. Millville will be a single core with 1 MB L2 cache only, so basically half an Allendale chip.
Kentsfield Will Be The First Desktop Quad Core
Intel currently is starting to place two single core processor dies into one package in order to create a dual core this way. This could be repeated in the future by combining two dual core dies.
The big news for the end of next year will be the first desktop processor product with four physical cores - although these are not going to be on a single die. Kentsfield is expected to hit the market in early or mid 2007. And yes, the code name is intended to be somewhat similar to Smithfield, since the target market segment is the same.
Obviously, a quad core processor with a decent amount of L2 cache would increase the transistor real estate by a tremendous amount. In order to avoid low yields due to huge die sizes, Kentsfield is referred to as coming in a multi chip package. This enables Intel to fit two or even more processor dies into a physical package while being able to select the particular parts beforehand. At the same time, the company will be able to answer changing demand highly flexible. Yet we could not get an answer on the question whether the Kentsfield's multi chip package will carry four Millville cores or two Allendale type chips. Both is doable why we expect it to be composed of two dual cores.
There will also be a server version of this dual core, code named Clovertown. Again it is 4 MB L2 cache and a multi chip package. The real surprise about the Kentsfield quad core product is the fact that is taped out already, which means nothing less than all the manufacturing parameters were provided to a manufacturing facility for first silicon. This, by the way, also happened with Allendale already.