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Besides AMD announcing faster speeds of their Athlon processor, which seems to be on a monthly basis, they have been pretty quiet lately. Even though the higher speed processors are exciting, everyone is still anxiously waiting for the next generation of Athlon supported chipsets. Right now AMD's current 750 chipset is a little behind the times. For one it lacks AGP 4X, which will be pretty important with the current and upcoming Transform and Lighting (T&L) based video boards. At the same time it cannot support the higher memory bandwidth that must accompany AGP 4X. Many of us are also still waiting for the final launch of an Athlon-chipset with support of SMP (multi processor setups). AMD is working closely with VIA and Samsung, to name a few, on these next generation chipsets and if companies like VIA should be nice enough to find some time developing the next generation Athlon-chipset besides competing with Intel's i820, we might even see something in the next millennium. Besides cooperating with 3rd party chipset makers AMD has also been improving their own 750 chipset. Quietly the new feature within their Northbridge called "Super Bypass" was finally enabled.
Basically super bypass removes some unnecessary memory latencies between the main memory and CPU. How much of the memory latency does super bypass remove? AMD-documents claim that super bypass reduces the latency by no less than 25%! One of the primary goals for any chipset designer is to develop a chipset that can communicate to the different internal buses with the least amount of latencies for each transaction. Take a look at AMD 750 chipset diagram below.
The AMD-751 (north bridge) handles all the communication between the CPU, SDRAM (or main memory), AGP bus and the PCI bus. Amongst other things, the 751-chip contains the memory request organizer (MRO). The MRO controls all the traffic between the CPU, PCI, AGP, and memory buses. When Super Bypass is disabled, the MRO has to go through numerous stages before getting the data to and from the main memory. When it is enabled the MRO can skip some of these stages, thus eliminating unnecessary clocks, which in-turn speeds up the transaction. There are certain conditions that have to be met on both the AGP and PCI buses for the super bypass feature to function. I am told by AMD that during normal system operation super bypass is able to function between 90-95% of the time. That sounds like a pretty good hit rate to me. You are probably asking "Why did AMD wait till now to add this new feature?" Actually super bypass was slated to work in AMD's 750 chipset from the get-go. Unfortunately, the super bypass feature was broken in the earlier revision of the AMD 750 chipset.