Join Tom’s Hardware today
When Lip-Bu Tan became the CEO of Intel last year, it was clear that a lot was going to change at the company. Now, details of these changes are beginning to emerge. We already know that Lip-Bu Tan personally assesses and approves chip designs before tape outs, but as it turns out, he also wants designs to be bug-free and ready for mass production already with the A0 revision, something that the company's products have failed to do.
"One thing about timetable, I have a culture right now I have just implemented. It has to be A0 to production," said Lip-Bu Tan at JP Morgan's Global Technology, Media and Communications Conference. "A0 is when you tape out, first time pass. Intel does not have that culture, so I tell that, first time pass A0. B0, you keep your job. Anything above that, you are fired."
"So that culture people initially thought that I'm just joking, and now I started to implement, they started to say that, 'Okay, Lip-Bu, you are very serious, you really look into all the design, all the bugs that we've tried to fix, and then all the IP that we use. You make sure that we certify and make sure we do that before we go to tape-out,' and so those are kind of the culture we need to have," Tan said.
A0 is the very first manufactured version of a chip produced after the initial tape out and before any silicon fixes are implemented. First-pass success means that the chip boots, functions correctly, meets major specifications, no major redesign is needed, and the silicon is close to production quality (or of production quality). Achieving A0 success with a complex CPU design on an advanced node is extremely difficult, more so than with other types of processors with simpler designs and redundant features.
While Nvidia and some other companies indeed begin to mass produce A0 chips after the initial tape out and bring up, it often takes Intel more revisions to get rid of bugs and maximize performance and yield. For example, Intel's Xeon 'Sapphire Rapids' processor contained as many as 500 bugs, and it took Intel a dozen revisions to get rid of erratas and reach planned performance and decent yields. At the time, that chip had seen A0, A1, B0, C0, C1, C2, D0, E0, E2, E3, E4 and E5 steppings to fix the egregious number of bugs.
Tan's comments are a bit unusual for a CEO of a company of Intel's size, as he essentially says that Intel's prior engineering culture was lax, so he is improving internal execution discipline. Ultimately, Tan wants fewer respins, faster validation, and shorter development cycles.
Whether or not A0 success can be achieved by all of Intel's products remains to be seen. For example, Nvidia is known for incorporating various yield-boosting techniques into its complex GPUs (e.g., redundant logic and caches) to avoid stepping failures and costly respins. However, Intel's design approaches are different.
One of the ways to reduce risks is to use industry-standard silicon-proven IP blocks and heavily verify designs before taping them out. In addition, Intel engineers might have to make less risky design decisions to achieve first-time success. Such an approach may make Intel's produces less ambitious in general, but at least the company's business performance will be more predictable.
Follow Tom's Hardware on Google News, or add us as a preferred source, to get our latest news, analysis, & reviews in your feeds.
