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GlobalFoundries: Double Patterning to Reach 20 nm

As previously, the company anticipates a six-to-18 month migration time to this new node. However, there are hurdles that need to be overcome. GlobalFoundries product manager Wei Lii Tan specifically pointed to the requirement of "double patterning requirements and new process rules specific to 20 nm" in a blog post published on Monday. He also mentioned that moving beyond 20 nm will be a "bit more complex".

Double patterning was already demonstrated at the 32 nm node, but it appears that GlobalFoundries will not be able to skip this more expensive manufacturing process at the 20 nm node anymore and will need this approach to overcome the physical limits of 193 nm immersion lithography to create smaller chip structures. "Using double patterning overcomes lithography limitations to fully realize the potential of a 20 nm process by manufacturing alternate tracks of metal in two separate steps," Tan wrote. "Double patterning requires extra masks, along with a colorized layout decomposition process to determine how layout features will be mapped to masks. However, double patterning is primarily needed for lower metal layers, and is not required for every layer."

According to the company, 20 nm equipment is "nearing production readiness", even if "not all semiconductor design companies will be adopting 20 nm immediately".

Update: GlobalFoundries reached out to clarify that it had always accounted for double patterning at 20 nm and, as such, this will not have any affect on the existing roadmap towards that process.

  • southernshark
    It does not seem like GF can compete at this level.
    Reply
  • fulle
    Anyone else read this as "GF plans to cut corners on it's 20nm process to try to save money".
    Reply
  • dickcheney
    Thats it, AMD is dead...
    Reply
  • Even Intel needs to change to another method to overcome this. Why wouldn't GF think of that?
    Reply
  • madooo12
    so the problem isn't with intel too
    Reply
  • serendipiti
    fulleAnyone else read this as "GF plans to cut corners on it's 20nm process to try to save money".Not sure, but looks to me like "our 20nm chips will be more expensive than we thought"

    dickcheneyThats it, AMD is dead...AMD is not tied to GF, but yes, seems like another door locked to AMD as chip cost will rise at the 20nm node.

    Don't know but people look too pessimistic.
    Perhaps it's too soon to draw any conclusion... Could be possible that a more expensive process drives to better products.
    Perhaps they are saying: we are going the same way intel went, so our products should improve to a better performance level.


    Reply
  • atikkur
    thats good, so we can enjoy our current processor much longer.. take your time.
    Reply
  • hannibal
    Hmmm.. could Intel be so kind and sell production capasity to AMD? Now when AMD buys production capasity to anyone that can provide it. GF and TSMC at this moment. How about Intel? Hmmm I think that intel does not sell their production capasity to anyone, but It would be nice to see what would happen :-)
    Reply
  • wiyosaya
    According to this article, AMD is rumored to be done with GF, and none too soon, IMHO, with this announcement.

    And according to this article, AMD's 7000 series GPUs will be made at TSMC.

    I say a happy good bye to bad rubbish.
    Reply
  • TeraMedia
    Guys...

    What this means is that out of the 10-20 layers of metal on the chip (they were around 9 or 11 a while back; I expect that number has gone up substantially now), the bottom few - which are the ones that are the smallest and closest together (because higher levels cannot be small-featured due to surface bumpiness caused by lower-layer structures) - need to be manufactured as two masks instead of 1. The one problem I see with this is that if you need to have a single metal structure with two close-together features in it, that would require a portion of the structure would be in one mask, and a different portion would be in the other mask, and I don't know if the process can allow for that without causing excessive surface variation at the point of intersection. Is that actually a problem? I can't envision a scenario in which it would be. So ultimately this means that the circuit design tools need to create two masks instead of one, for a given low-level metal layer. The design tools already create multiple layers per mask anyway (positives, negatives, intersections with vias, etc.), so not really a huge issue. Either Intel ran into this too (and notice you didn't hear about it...), or they employ a different technology to lay down and mask their metal layers. I suspect the former.

    This does mean that existing masks cannot simply be scaled down, however. So an IC designer such as AMD cannot simply send the same mask binaries and request a smaller process size. Instead, they need to regenerate the mask binaries using the new process rules. Chances are, other differences in the new process would have necessitated this anyway, so again, no big deal.
    Reply