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• Intel Developer Forum, Day One: Intel Thinks Small

  Things small include the next-generation desktop microarchitecture Intel is calling Sandy Bridge. If Westmere represents the transition of Nehalem’s architecture to 32nm, Sandy Bridge is the “tock”--a new microarchitecture on an existing process technology. It’s odd to call 32nm “existing,” but Intel has already built a boatload of 32nm CPUs already. Not much was revealed about the specifics of Sandy Bridge, however. Taking a step down the size scale to mobile platforms, Intel showed off Clarkdale, the 32nm mobile CPU that will offer an on-package graphics chip. Clarkdale, as with the current Core i7’s, will support Hyper-Threading, though it will have only two cores, rather than four. Clarkdale (in addition to all other Westmere-based products) features hardware-assisted AES encryption. Historically, the problem with high levels of encryption has been the performance hit incurred when encrypting or decrypting in real time. Intel hopes that its AES-NI (AES New Instructions) will enable more widespread use of encryption software. As mobile platforms become the mainstay of most computing users, the fear of losing valuable data to identity thieves increases. Intel showed one demo where a stolen laptop could be deactivated over the Web with the encrypted hard drive rendered completely inaccessible until the laptop is brought back to its IT department. One aspect of this focus is the Atom. Atom has become pretty popular for netbooks, but Intel’s real target market for Atom has always been mobile Internet devices and smart phones. The current-generation Atom isn’t well-suited for smaller devices like cell phones, which require extensive battery life and don’t (yet) need multi-GHz speeds. However, as the process technology moves to 32nm, the next-generation Atom (code-named Moorestown) will be built on smaller boards and offer greater integration than today’s Atom. Idle power will be considerably reduced, too--up to 50x lower power draw at idle than the Atom we now know. The whole affair is still a bit too large for all but the biggest smart phones, but as Atom becomes even smaller in the generation beyond Moorestown (code-named Medfield) Atom may be small enough for pretty small phones. Beyond 32nm While we’re talking about small, let’s talk 22nm. At one point during the morning keynote, Intel CEO Paul Otellini held up a wafer consisting of 22nm test SRAM chips. With 32nm CPUs just around the corner, Intel is already starting to push new technologies. In the tick-tock mode, Westmere is now practically old hat. Intel is starting to talk up its true next-generation microarchitecture, Sandy Bridge. On the process side, Intel displayed a wafer of SRAM (static RAM) test chips built on a 22nm manufacturing process, including its 3rd generation high-k plus metal gate technology. The 22nm SRAM chip has 0.092 um2 SRAM cells for high-density SRAMs, and 0.108 um2 for low voltage apps. The 0.092nm cell is the smallest working chip to date. Although it is an SRAM test chip, there are some logic circuits built onto the chip to test the process technology as it might be used to build actual microprocessor logic. Intel’s code name for the process for building CPUs is P1270; P1271 is the manufacturing process that will be used for SoC (system-on-chip) processors, including next-generation Atom processors. The “12” implies 12-inch wafer sizes; current tools don’t really allow Intel to move to larger wafer manufacturing sizes in the near term. One of the interesting aspects of Intel’s focus on process technology and Moore’s Law is the implications on the evolution of instruction sets and chip size. One slide from the afternoon keynote noted how the original Intel 4004 had about 70 instructions, whereas the current generation of Nehalem CPUs now have over 700 instructions. And, of course, that Nehalem CPU is physically no larger, even though the transitor count is vastly greater.

• In order run physics effects on your PC today, you typically have to use the CPU, regardless of the platform you rely on. IBM's Xenon & Broadway, Sony Cell, Intel Core or AMD Phenom - all of these CPUs, however, have not yet shown that they can be capable physics drivers, so, in our opinion, specialized physics accelerators will be the solution for the future. Even at Intel there is Larrabee, which is designed to become an all-purpose accelerator chip that is used for graphics as well as ray-tracing and physics, according to sources close to company. The second part of the equation is the development of next-generation game engines, which are going to drive implementation of real-world physics with next-generation consoles and PCs. Let's look the public statements made in regards to the Nvidia-Ageia deal: Nvidia released a following statement from Jen-Hsun Huang, co-founder and CEO: "The AGEIA team is world class, and is passionate about the same thing we are - creating the most amazing and captivating game experiences. By combining the teams that created the world's most pervasive GPU and physics engine brands, we can now bring GeForce-accelerated PhysX to hundreds of millions of gamers around the world." Manju Hegde, co-founder and CEO of Ageia, released the following statement: "Nvidia is the perfect fit for us. They have the world's best parallel computing technology and are the thought leaders in GPUs and gaming." True or not, the two statements refer to the present situation. But this deal was all about the future and controlling (or at least balancing) the world of physics computing, which set to march beyond the domain of games. Based on these statements, you might think that all currently-shipped GeForce products support PhysX, while the truth is that PhysX will be implemented in future chips, destined to be shipped in the hundreds of millions. Suddenly there is a pretty good reason for developers and publishers to jump on PhysX immediately. Following the acquisition yesterday, we had the chance to talk to Tim Sweeney, founder of Epic Games and the brain behind the Unreal engine. Sweeney said that "we've had a great relationship with the Ageia team for years, and bundle their PhysX library with Unreal Engine 3 as its standard physics solution." He added that he was "happy to see Nvidia jump in and throw its massive weight behind physics." Sweeney mentioned that he is planning to use Ageia physics features with "future Unreal Engine 3 games on all platforms." The "all platforms" note is particularly interesting. Hidden away from the eyes of public, engineers are creating next-generation Xbox, next-gen PlayStation and next-gen Wii titles. We managed to find out that all creative spirits of these projects are now hidden in caves, working hard on getting the new silicon for future parts. You can expect that new wave of consoles comes will come to market in the 2010/11 timeframe, even though conservative estimates are talking about 2012 at this point. But, clearly, Nvidia's mention of "hundreds of millions of gamers" was a signal for the IT industry as whole. It will be driven in all major graphics application markets. When it comes to PC itself, Nvidia has several plans, seen in this author's 2nd grade MSPaint skills in the picture above. The future is in physics being rendered on Nvidia's integrated chipsets and graphics cards. The key to this strategy is not to think just about Intel or AMD processors, but a bit wider than that. If we are listening to the "rumors that could be true" department, we should to pay attention to the next-generation Sony console, which may integrate physics capability directly into Nvidia's GPU, which reportedly is not going to be the last-minute patchwork Nvidia had to deliver with the PS3 RSX GPU. What makes this deal a sensible solution is the fact that Ageia has the engineers to take advantage of Nvidia's future hardware. You can bet the farm on the fact that future GPUs will have substantial input from Ageia's staff in terms of effectively channeling: Current GPUs have a deadly flaw in GPGPU terms - there are substantial performance penalties when branching is used. At the other hand, CPU and PPU excel in branching, because there is enough cache to put "what-if" instructions and correctly predict what could happen. Intel knew that and is building Larrabee with massive cache in the middle, while Nehalem, Westmere and Sandy Bridge will continue to increase the overall amount of cache, while re-introducing Hyper-Threading, enabling up to 16 threads on a single socket. It is too early to say what will be the first GPU influenced by Ageia's engineers, but we expect that some influence might already be seen in the high-end graphics chip coming in 2009.

• For starters, Intel is prepared for battle. The company paid a hefty price for Havok, but it had a one-year head start and its ace remains the Westmere/Sandy Bridge CPU in combination with the Larrabee cGPU. AMD will integrate the GPU with a CPU in a project named Fusion, but the company has a Lego block approach, so additional computing units are not excluded. Right now, it looks to us that Nvidia may have made just another smart acquisition and Ageia could turn out to be another 3dfx or ULi Technologies, companies Nvidia ate ages ago. Gamers will now get hardware physics, Nvidia gets another set of technologies to toy with, and the competition is more than alive. Cards are dealt and the game is about to begin.