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Intel Patents Forming MP Chips Using Dual Processors

By - Source: USPTO | B 31 comments

Intel has received a patent covering its technology to create multi-core processor packages from individual dual-core processors.

Filed in April 2007, the patent describes a replication of entire processors by creating point-to-point link logic between the multi-core processors. Specifically, the patent describes a design approach that delivers a much faster time to market and less complexity as this patent does not rely on modified processing protocols or significant hardware design changes.

Illustrations included in the patent reveal that Intel's multi-chip package can be created simply by using an intra-package interconnect as point-to-point link with short trace length that allows for a shorter and wider bus as well as higher clock speeds to achieve substantial bandwidth between the two processors. According to Intel, that link can be established via interconnects that are already available on the substrate.

Additionally, Intel is using a "protocol joining method" to figure out the number of necessary caching agents and home agents in the system. Additional caching agents are treated as independent caching domains and the burden of managing coherence between the two caches relies on the point-to-point cache coherency domain.

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  • 17 Hide
    madooo12 , May 7, 2012 4:39 PM
    Parsianisnt this the method they used to make the Core 2 Quads?

    Quote:
    Filed in April 2007
  • 10 Hide
    Parsian , May 7, 2012 4:36 PM
    isnt this the method they used to make the Core 2 Quads?
Other Comments
  • 10 Hide
    Parsian , May 7, 2012 4:36 PM
    isnt this the method they used to make the Core 2 Quads?
  • 17 Hide
    madooo12 , May 7, 2012 4:39 PM
    Parsianisnt this the method they used to make the Core 2 Quads?

    Quote:
    Filed in April 2007
  • 6 Hide
    husker , May 7, 2012 4:58 PM
    It does appear to simplify the architecture, but this type of simplification usually comes at a cost of speed and efficiency. I'm wondering if it will scale well with a large number of processors since it requires a point to point link between all processors this could get out of hand in a hurry.
  • 4 Hide
    ojas , May 7, 2012 4:59 PM
    Parsianisnt this the method they used to make the Core 2 Quads?

    Probably been using it already, just that the patent was granted now.
  • 4 Hide
    eddieroolz , May 7, 2012 5:01 PM
    huskerIt does appear to simplify the architecture, but this type of simplification usually comes at a cost of speed and efficiency. I'm wondering if it will scale well with a large number of processors since it requires a point to point link between all processors this could get out of hand in a hurry.


    That may have been true for the days of FSB that were bottlenecking single processors, let alone dual. However, with the days of QPI buses this might not be such a big issue.
  • -6 Hide
    DjEaZy , May 7, 2012 5:12 PM
    ... it's like hypertransport in a sense...
  • 3 Hide
    bigdog44 , May 7, 2012 5:15 PM
    The first diagram looks like a pentagram on homebase... is SIntel patenting its' business model?
  • 4 Hide
    willard , May 7, 2012 5:18 PM
    DjEaZy... it's like hypertransport in a sense...

    Yeah, in the same way that a car is like a road.

    Hypertransport is a method of interconnecting chips. This patent is for what you can do with interconnected chips.
  • -6 Hide
    madooo12 , May 7, 2012 5:34 PM
    bigdog44The first diagram looks like a pentagram on homebase... is SIntel patenting its' business model?

    can you patent to be evil, a big monopoly and an anti-competitive company? don't answer that
  • 1 Hide
    husker , May 7, 2012 6:14 PM
    eddieroolzThat may have been true for the days of FSB that were bottlenecking single processors, let alone dual. However, with the days of QPI buses this might not be such a big issue.

    Good point.
  • -4 Hide
    doive1231 , May 7, 2012 6:15 PM
    This will stop AMD in their tracks.
  • 0 Hide
    blazorthon , May 7, 2012 7:01 PM
    Intel used this method for Core 2 Quads and the Xeons of the time. In fact, Intel has been using this for their Nehalem CPUs with more than 4 cores and more. Guess what? AMD does it too. AMD does this for the Magny-Cours and Interlagos Opterons. So, is AMD going to get a big FU in the mail from Intel soon, inviting AMD to a party in a court house with this as the theme?
  • 3 Hide
    blazorthon , May 7, 2012 7:02 PM
    blazorthonIntel used this method for Core 2 Quads and the Xeons of the time. In fact, Intel has been using this for their Nehalem CPUs with more than 4 cores and more. Guess what? AMD does it too. AMD does this for the Magny-Cours and Interlagos Opterons. So, is AMD going to get a big FU in the mail from Intel soon, inviting AMD to a party in a court house with this as the theme?


    Intel also used it for their dual core Netburst chips.
  • 5 Hide
    ProDigit10 , May 7, 2012 7:35 PM
    oh no, it's a demon star ring bus!
  • 3 Hide
    nukemaster , May 7, 2012 8:30 PM
    Some of this DOES look allot like AMD's NUMA setup.

    Now here Intel seems to be doing thing different(Not using HT and using the cpu substrate).

    This is far more then just joining cpus.
  • 4 Hide
    elbert , May 7, 2012 8:38 PM
    I don't see how Intel can patent reed's Law for full interconnection. This looks to me like a mesh topology with a star network topology to the ICH. I can see why these methods are used due to similar nature for more cores or PC but why make them out to be something new.
  • 2 Hide
    blazorthon , May 7, 2012 9:28 PM
    nukemasterSome of this DOES look allot like AMD's NUMA setup.Now here Intel seems to be doing thing different(Not using HT and using the cpu substrate).This is far more then just joining cpus.


    Interlagos is two Valencia 4, 6, or 8 core dies connected to each other in a single package, just like Core 2 Quads and the other examples that I listed. It's the same as this patent, except the bus interface (QPI vs. HT) is different and maybe a few other minor differences.
  • 1 Hide
    A Bad Day , May 7, 2012 9:28 PM
    huskerIt does appear to simplify the architecture, but this type of simplification usually comes at a cost of speed and efficiency. I'm wondering if it will scale well with a large number of processors since it requires a point to point link between all processors this could get out of hand in a hurry.


    I suppose it works fairly well when you have like 2-4 processors. Once you go past like a dozen of processors with the point-to-point system, you're going to need lots of wiring and anti-crosstalk measures.
  • 1 Hide
    blazorthon , May 7, 2012 9:44 PM
    A Bad DayI suppose it works fairly well when you have like 2-4 processors. Once you go past like a dozen of processors with the point-to-point system, you're going to need lots of wiring and anti-crosstalk measures.


    Make it more modular. Up to four processors could be a single linked up group and then up to 16 could be a linked group of four modules and so on. That could help it a little.
  • 0 Hide
    jimmysmitty , May 7, 2012 10:11 PM
    blazorthonIntel used this method for Core 2 Quads and the Xeons of the time. In fact, Intel has been using this for their Nehalem CPUs with more than 4 cores and more. Guess what? AMD does it too. AMD does this for the Magny-Cours and Interlagos Opterons. So, is AMD going to get a big FU in the mail from Intel soon, inviting AMD to a party in a court house with this as the theme?


    Thats not quite right. Westmere was the first 6 core from Intel, it was a 32nm die shrink of Nehalem. It was a monolithic die, not MCM like Core 2 Quad or Pentium D.

    Nehalem-EX was the first 8 core CPU and it as well is also a monolithic design, not MCM. In fact Nehalem EX is currently Intels largest CPU in terms of die size and amount of cores in the CPU itself. None of Intels current CPUs are MCM, they have SMT which allows multiple threads per core but thats it.

    AMDs 12 core is two Thuban 6 cores in a MCM package much like Core 2 Quad but Intel is not going to do that again for a while, except with possibly Haswell and the L4 Cache.
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