Intel Patents Forming MP Chips Using Dual Processors
Intel has received a patent covering its technology to create multi-core processor packages from individual dual-core processors.
Filed in April 2007, the patent describes a replication of entire processors by creating point-to-point link logic between the multi-core processors. Specifically, the patent describes a design approach that delivers a much faster time to market and less complexity as this patent does not rely on modified processing protocols or significant hardware design changes.
Illustrations included in the patent reveal that Intel's multi-chip package can be created simply by using an intra-package interconnect as point-to-point link with short trace length that allows for a shorter and wider bus as well as higher clock speeds to achieve substantial bandwidth between the two processors. According to Intel, that link can be established via interconnects that are already available on the substrate.
Additionally, Intel is using a "protocol joining method" to figure out the number of necessary caching agents and home agents in the system. Additional caching agents are treated as independent caching domains and the burden of managing coherence between the two caches relies on the point-to-point cache coherency domain.


Probably been using it already, just that the patent was granted now.
That may have been true for the days of FSB that were bottlenecking single processors, let alone dual. However, with the days of QPI buses this might not be such a big issue.
Yeah, in the same way that a car is like a road.
Hypertransport is a method of interconnecting chips. This patent is for what you can do with interconnected chips.
can you patent to be evil, a big monopoly and an anti-competitive company? don't answer that
Good point.
Intel also used it for their dual core Netburst chips.
Now here Intel seems to be doing thing different(Not using HT and using the cpu substrate).
This is far more then just joining cpus.
Interlagos is two Valencia 4, 6, or 8 core dies connected to each other in a single package, just like Core 2 Quads and the other examples that I listed. It's the same as this patent, except the bus interface (QPI vs. HT) is different and maybe a few other minor differences.
I suppose it works fairly well when you have like 2-4 processors. Once you go past like a dozen of processors with the point-to-point system, you're going to need lots of wiring and anti-crosstalk measures.
Make it more modular. Up to four processors could be a single linked up group and then up to 16 could be a linked group of four modules and so on. That could help it a little.
Thats not quite right. Westmere was the first 6 core from Intel, it was a 32nm die shrink of Nehalem. It was a monolithic die, not MCM like Core 2 Quad or Pentium D.
Nehalem-EX was the first 8 core CPU and it as well is also a monolithic design, not MCM. In fact Nehalem EX is currently Intels largest CPU in terms of die size and amount of cores in the CPU itself. None of Intels current CPUs are MCM, they have SMT which allows multiple threads per core but thats it.
AMDs 12 core is two Thuban 6 cores in a MCM package much like Core 2 Quad but Intel is not going to do that again for a while, except with possibly Haswell and the L4 Cache.