So Many Semprons

Unlike the Athlon 64 family, the Sempron line for Socket 754 is still simple enough to keep track of:

The first Sempron processor available was the 3100+, based on the 130 nm Paris core (CG). This was AMD's introduction of its new low-cost CPU family. Oakville (D0 revision) was the first 90 nm Sempron, introduced in April 2005. All Oakville cores come with 256 kB of L2 cache and SSE3 support, but only certain models use all of that L2 cache - the Sempron 2600+, 3000+ and 3300+ utilize 128 kB only.

Today's introduction of the Sempron 3400+ brings us another core that is still based on 90 nm fabrication, but introduces into the Sempron line the improved memory controller we already know from the Athlon 64 Venice and San Diego cores. Another addition to the core (E3 and E6 revision) is the SSE3 instruction set that Intel introduced in early 2004 . Palermo will be available for all the slower speed grades, but AMD64 won't be enabled for the time being.

One note about Cool & Quiet: AMD enables this feature only for models rated 3000+ and faster. It requires a processor driver (downloadable from AMD's website) and when enabled, allows the operating system to reduce the clock speed in several increments to save energy and reduce heat dissipation. This is completely different from Intel's strategy, because both the desktop and the mobile Celeron D processors are not capable of dynamically changing the clock speed. Only Pentium 4 600 processors at 3+ GHz and Pentium M CPUs implement SpeedStep.