Thinking up a kewl name is one thing, but equipping the new processor with the 'optimum' technology is another. There is no reason to worry, however. AMD was able to pack some really nifty stuff into its upcoming new "Opteron" processor.

• Integrated Memory Controller (!!)
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  The probably most promising feature of AMD's Opteron processors will be the integrated memory controller. Unlike what's found in x86 systems today, Opteron does not require to go through the chipset's "north bridge" when accessing memory. Rather than that, the Opteron processor hooks up directly to the memory, and because it is a 64-bit (as well as 32-bit) processor, it also comes with a wider memory bus of 128-bit width - something we so far knew from 3D chips only. What you get is a direct connect from Opteron to two parallel 64-bit wide memory interfaces as we know them today. This doubles the memory bandwidth and the omission of a north bridge chip in between reduces latency as well. Things get even better. In SMP (multi processor) systems, each Opteron has its own memory interface and its own memory. This might have been overkill in the past, but with memory prices as low as today, this solution is feasible and most certainly the best way to go in terms of performance, as it offers a whopping bandwidth of up to 5.3 GB/s per processor.
  There is one rather serious disadvantage of this integrated memory controller though. It is only designed for one type of memory. It is not surprising that AMD chose a DDR-SDRAM interface (clocked at 266-333 MHz), which is clearly showing the best future right now. However, RDRAM or QDR-SDRAM will not be supported. It would require a redesign of Opteron's processor die. Still, it might well be possible that future Opteron processors come in different flavors for different memory types.
• x86-64 Technology
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  Much has already been said about the Sledgehammer core and AMD's approach to 64-bit processing, so I will keep myself short on this. Unlike Intel's "Itanium" processor, which 'understands' only IA64 software and which is not backwards compatible to the Pentium1-4 32-bit processors of today and yesterday, Opteron will "understand" today's 32-bit software as well as future x86-64 64-bit software. Opteron executes both software types natively and thus with full speed. This gives users the opportunity to stick with 32-bit software for the time being, saving the costs of a complete software revamp and still leaves the chance for a future 'upgrade' to 64-bit software without having to buy a new platform. Microsoft has just announced that it will support x86-64, so there will be WindowsXP and MS Office for Opteron's 64-bit instruction set as well.
• HyperTransport Technology
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  HyperTransport itself is not new whatsoever and latest since NVIDIA put Hypertransport into its nForce chipset, everyone with a technical interest is well aware of its virtues. With Opteron, AMD is taking the usage of HyperTransport to a new level. 16 CAD HyperTransport (16-bit wide, CAD=Command, Address, Data) will be used as the interface for processor-to-processor and processor-to-chipset, providing a bandwidth of up to 6.4 GB/s and thus about 50% more than what the latest Pentium 4 or Xeon processors with 533 MHz processor bus clock are able to provide. For the techies of you, the 6.4 GB/s are exactly 3.2 GB/s in each direction, while the 16-bit wide interface is clocked at 800 MHz and transporting data at double data rate. Sounds all very 'Rambus' to me, but it's not a memory interface after all. 8-bit wide HyperTransport (bandwidth up to 1.6 GB/s with 400 MHz clock) will be used to interconnect Opteron-system components that don't require the ultra-high bandwidth provided by the 16-bit version, such as normal I/O-Hubs.
• Large 2nd Level Cache
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  It is not suprising that AMD will offer Opteron with up to 1 MB of L2 cache, which is particularly useful in enterprise server systems. Workstations are usually not able to benenfit too much from L2 caches of that size.

AMD predicts that Opteron will have a nominal performance gain over Athlon of about 25% (at equal clock speeds), where 20% are coming from Opteron's new intergrated low-latency memory interface and 5% from improvements to Opteron's core.