By rendering a single physical processor to serve as two processors, HT represents a departure from traditional CPU processor performance improvements involving either boosting the clock speed or cache designs.

HT provides a second logical processor in a single physical package so there are two separate logical architectures that also share only one set of physical execution resources. From a software or architecture perspective, this means operating systems and user programs can schedule processes or threads to logical processors as they would on conventional physical processors in a multiprocessor system. From a microarchitecture perspective, this means that instructions from logical processors will persist and execute simultaneously on shared execution resources.

With two copies of the architectural state on each physical processor, the system appears to have four logical execution units, branch predictors, control logic, and buses.

Each logical processor has its own interrupt controller. Interrupts sent to a specific logical processor are handled only by that logical processor.