SiS 5600/5595
The new Slot-1 chipset from SiS consists of the north bridge 5600 in a BGA package and the south bridge 5595. A single chip solution would have been even cheaper, but it seems as if this isn't possible yet. Let's take a look at the technical data:
5600 North Bridge
- 487-ball BGA package, 3.3V CMOS
- up to 100 MHz FSB support
- support for single Pentium II or Celeron CPUs
- integrated DRAM controller supports SDRAM, EDO and even FPM memory as well as ECC (max. 768 MB), 3/6 memory banks (double/single sided)
- AGP 1x or 2x interface
- Supports SideBand Addressing (SBA) mode
- Max. 4 PCI busmaster slots
- Integrated PCI EIDE controllers (PIO mode 4 or UltraDMA mode 2)
- PC98 compliant
5595 South Bridge
- 208-pin PQFP package, 0.5V CMOS
- PCI-to-ISA bridge
- ACPI 1.0 and APM 1.2 compliant
- Suspend-to-RAM and suspend-to-disk supported
- USB interface, 2 ports
- SB link and I²C serial bus supported
- ISA bus interface, IRQ and DMA controller, timer, real time clock and keyboard and PS/2 mouse controller
- Voltage (5x), temperature (1x) and fan (2x) monitoring capability
- Support for real time clock and LAN wake up
- Jumperless CPU core frequency setting supported
The data sounds promising. Integrating the keyboard controller saves costs and room on the motherboard. The memory controller also supports EDO and even FPM memory which does only work in case of 66 MHz FSB, but leaves open all paths of equipping memory. I would really like to see a Pentium II motherboard offering the option of clocking the main memory asynchronously to run the Pentium II over 333 MHz at 66 MHz memory clock. As you've seen in our review regarding the AMD K6-2's performance at different bus and memory speeds, the most performance relevant factor is the L2 cache speed, not the memory clock speed. The same applies to Slot-1 CPUs. Only the "old" Celeron without L2 cache would lose performance considerably, but for Pentium II users such an option would be great.
