AMD Allegedly Testing Hybrid Processor with Zen 4 and 4c Cores

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AMD's first Big.Little-like processor may be just around the corner.

An unannounced AMD processor identified as Family 25 Model 120 Stepping 0 recently showed up in the MilkyWay@Home database. The CPU can process 12 threads simultaneously and the CPU expert @InstLatX64 believes that this is AMD's codenamed Phoenix 2 processor, packing two high-performance Zen 4 cores and four energy-efficient Zen 4c cores. 

AMD Eng Sample processor marked 100-000000931-21_N [Family 25 Model 120 Stepping 0] features 12 logical cores (i.e., six physical cores with simultaneous multithreading) and reports about 1MB of cache, which indicates that the MilkyWay@Home client cannot correctly determine the amount of cache featured by the chip. The listing itself does not prove that we are dealing with AMD's hybrid Phoenix 2 processor with Big.Little-like core configuration, but six physical/12 logical cores featured by an unknown CPU gives us a hint that this may match the rumors.

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Anton Shilov
Anton Shilov
Contributing Writer

Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.

57 Comments Comment from the forums
  • zecoeco
    AMD is cooking some hybrid Zen 5 CPUs...
    It'll be interesting to see who'll come at top.
    Between Arrow-Lake and Zen 5.
    Reply
  • jkflipflop98
    That will be a good fight, but that's peanuts compared to what comes after. Everything is going to change soon. Everything.
    Reply
  • ezst036
    I like the big.little concept the more I think about it. I used to dislike it very strongly.

    It makes sense for a majority of work to be done on the most low power cores they can make, and only brute force whatever needs it at the time it needs it such as when gaming or using Blender. This is, to some extent, how ARM achieves its goals.

    It's also a win for the manufacturers because of the needs of die space in a fab.
    Reply
  • DaveLTX
    ezst036 said:
    I like the big.little concept the more I think about it. I used to dislike it very strongly.

    It makes sense for a majority of work to be done on the most low power cores they can make, and only brute force whatever needs it at the time it needs it such as when gaming or using Blender. This is, to some extent, how ARM achieves its goals.

    It's also a win for the manufacturers because of the needs of die space in a fab.
    In particular it's great if the ISA and cores are truly heterogenous, in the case of ARM that failed to be the case with X2, A710 and A510 with only A710 supporting 32 bit iirc
    With AMD all cores support AVX512 and since the caches take up majority of the space, it cuts down by half compared to Zen 4 while delivering almost identical IPC unless it heavily requires the L3 cache. It's almost half the size!
    (L2, the main thing increased with zen 4 stays the same for Zen 4c per core)

    Where I'm guessing AMD is going to take is 8 zen 4 CCD and 16 core zen 4c CCD for the big am5 options. Considering the massive ipc advantage zen 4 has over gracemont cores (especially with vector workloads) this could be a serious fight and the fact that it has a L3 which gracemont doesnt have but kind of has, but it has to go all the way round the CPU to nest into. This is a situation where gracemont truly are low performance cores... (Way below peak IPC, and they suck at power efficiency anyway to begin with)
    Reply
  • PC Hardware Nerd
    DaveLTX said:
    In particular it's great if the ISA and cores are truly heterogenous, in the case of ARM that failed to be the case with X2, A710 and A510 with only A710 supporting 32 bit iirc
    With AMD all cores support AVX512 and since the caches take up majority of the space, it cuts down by half compared to Zen 4 while delivering almost identical IPC unless it heavily requires the L3 cache. It's almost half the size!
    (L2, the main thing increased with zen 4 stays the same for Zen 4c per core)

    Where I'm guessing AMD is going to take is 8 zen 4 CCD and 16 core zen 4c CCD for the big am5 options. Considering the massive ipc advantage zen 4 has over gracemont cores (especially with vector workloads) this could be a serious fight and the fact that it has a L3 which gracemont doesnt have but kind of has, but it has to go all the way round the CPU to nest into. This is a situation where gracemont truly are low performance cores... (Way below peak IPC, and they suck at power efficiency anyway to begin with)
    I would love to see a chip like that. All the cores support 2 threads so that's 48 threads of zen4 power in a desktop chip. Wild.
    Reply
  • bit_user
    I think this shows AMD is worried about Meteor Lake.

    DaveLTX said:
    Where I'm guessing AMD is going to take is 8 zen 4 CCD and 16 core zen 4c CCD for the big am5 options.
    I think this is primarily aimed at laptops, where they'll probably go with a monolithic die for energy-efficiency reasons.

    Then again, maybe their recent advancements in chiplet communication efficiency, that we saw in RDNA3, will enable them to use chiplets for mainstream laptop CPUs.
    Reply
  • usertests
    We've seen leaks of Zen 5 + Zen 4C chiplets for Granite Ridge many months ago. This thing, "Little Phoenix", was also leaked months ago.

    With 2x Zen 4 (low clocks?) + 4x Zen 4C + unknown CUs (4?), it wouldn't be clearly better than some discounted Barcelo/Rembrandt options. I'm seeing it as a successor to Mendocino at the premium price points that was supposed to target ($400-700) while Mendocino is relegated to sub-$250 laptops. I guess it could target the same TDPs as Mendocino, especially with a node shrink and other tricks to reduce power. Slash the cache on some cores and lower the clock speeds, and you get the very efficient 'C' version. AMD has already tried mixed cache with 7000X3D.

    I think this will be monolithic, no chiplets.
    Reply
  • digitalgriffin
    God now I'm going to end up doing more paper napkin math.

    Quit giving me ideas guys.
    Reply
  • jeremyj_83
    DaveLTX said:
    Considering the massive ipc advantage zen 4 has over gracemont cores
    IIRC Bergamo, Zen4c in server CPUs, each core is supposed to have performance around Zen 3. Gracemont has performance of about Skylake. Zen 2's IPC was 7-10% higher than Skylake and Zen 3 is another 15% over Zen 2. Based on that we could expect Zen4c's IPC to easily be 25-30% higher than Gracemont. I assume that Zen4c would be easier to clock higher as well. This could be an interesting setup as you still would have full fat cores just lower performing. It would be more like the newer Arm big.little with 4 high performance cores but 2 are clocked higher than another 2.
    Reply
  • TJ Hooker
    DaveLTX said:
    In particular it's great if the ISA and cores are truly heterogenous, in the case of ARM that failed to be the case with X2, A710 and A510 with only A710 supporting 32 bit iirc
    With AMD all cores support AVX512 and since the caches take up majority of the space, it cuts down by half compared to Zen 4 while delivering almost identical IPC unless it heavily requires the L3 cache. It's almost half the size!
    It seems like you mean "homogeneous", not "heterogeneous".
    Reply