VT82C580VP APOLLO VP-1

Features

• PCI/ISA Green PC Ready
• High Integration
• VT82C585VP system controllerVT82C586 PCI to ISA bridgeTwo instances of the VT82C587VP data buffersSix TTLs for a complete main board implementation
• Flexible CPU Interface
• 64 bit PentiumTM, AMD5K 86TM and Cyrix6X 86TM CPU interfaceCPU external bus speed up to 66/75 MHz (internal 200 MHz and above)Supports CPU internal write-back cacheConcurrent CPU/cache and PCI/DRAM operationSystem management interrupt, memory remap and STPCLK mechanismCyrix6X 86 linear burst supportCPU NA#/Address pipeline capability
• Advanced Cache Controller
• Direct map write back or write through secondary cacheBurst synchronous (pipelined or non-pipelined), asynchronous SRAM, and Cache Module supportEight-pin CWE# and GWE# control optionsFlexible cache size: 0K/256K/512K/1M/2 MB32 Byte line size to match the primary cacheIntegrated 10 bit tag comparator3-1-1-1 read/write timing for Burst Synchronous SRAM access at 66/75 MHz3-1-1-1-1-1-1-1 back to back read timing for Burst Synchronous SRAM access at 66/75 MHzSustained 3 cycle write access for Burst Synchronous SRAM access or CPU to DRAM and PCI bus post write buffers at 66/75 MHzData streaming for simultaneous primary and secondary cache line fillSystem and video BIOS cacheable and write-protectProgrammable cacheable region and cache timing
• Fast DRAM Controller
• Concurrent DRAM writebackFour Cache lines (16 quadwords) of CPU/cache to DRAM write buffersFast Page Mode/EDO/Burst EDO/Synchronous-DRAM support in a mixed combinationMixed 1M/2M/4M/8M/16MxN DRAMs6 banks up to 512 MB DRAMs (maximum four banks of Synchronous DRAM)Flexible row and column addresses64 bit or 32 bit data width in arbitrary mixed combination3.3v and 5v DRAM without external buffersSpeculative DRAM accessRead around Write capability for non-stalled CPU readBurst read and write operation4-2-2-2 on page, 7-2-2-2 start page and 9-2-2-2 off page timing for EDO DRAMs at 50/60 MHz5-2-2-2 on page, 8-2-2-2 start page and 11-2-2-2 off page timing for EDO DRAMs at 66/75 MHz5-1-1-1 on page, 8-1-1-1 start page and 10-1-1-1 off page for Burst EDO and SDRAMs at 66/75 MHz5-2-2-2-3-1-2-2 back-to-back access for EDO DRAM at 66/75 MHz5-1-1-1-3-1-1-1 back-to-back access for BEDO and SDRAM at 66/75 MHzBIOS shadow at 16 kB incrementDecoupled and burst DRAM refresh with staggered RAS timingProgrammable refresh rate, CAS-before-RAS refresh and refresh on populated banks only
• Unified Memory Architecture
• Supports VESA UMA handshake protocolCompatible with major video/GUI productsDirect video frame buffer accessSatisfies maximum latency requirement from REQ# to GNT# and from GNT# to REQ#
• Intelligent PCI Bus Controller
• 32 bit 3.3/5v PCI interfaceSynchronous divide-by-two with extension to asynchronous PCI bus interfacePCI master snoop ahead and snoop filteringPCI master Peer ConcurrencyAutomatic detection of data streaming burst cycles from CPU to the PCI busFive levels (doublewords) of CPU to PCI posted write buffersByte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilitiesZero wait state PCI master and slave burst transfer ratePCI to system memory data streaming up to 132 MByte/secSixty-four levels (doublewords) of post write buffers from PCI masters to DRAMThirty-two levels (doublewords) of prefetch buffers from DRAM for access by PCI mastersEnhanced PCI command optimization (MRL, MRM, MWI, etc.)Complete steerable PCI interruptsSupports L1 write-back forward to PCI master read to minimize PCI read latencySupports L1 write-back merged with PCI master post-write to minimize DRAM utilizationProvides transaction timer to fairly arbitrate between PCI mastersPCI-2.1 compliant
• Enhanced Master Mode PCI IDE Controller with Extension to ATA-33
• Dual channel master mode PCI supporting four Enhanced IDE devicesTransfer rate up to 22 MB/sec to cover PIO mode 4 and Multiword DMA mode 2 drivers and beyondExtension to ATA-33 interface for up to 33 MB/sec transfer rateSixteen levels (doublewords) of prefetch and write buffersInterlaced commands between two channelsBus master programming interface for SFF-8038 rev.1.0 and Windows-95 compliantFull scatter and gather capabilitySupport ATAPI compliant devicesSupport PCI native and ATA compatibility modesComplete software driver support
• Universal Serial Bus Controller
• USB v1.0 and Intel Universal HCI v1.1 compatibleEighteen levels(doublewords) of data FIFOsRoot hub and two function ports with built-in physical layer transceiversLegacy keyboard and PS/2 mouse support
• Plug and Play Controller
• Dual interrupt and DMA signal steering with plug and play controlMicrosoft Windows 95TM and plug and play BIOS compliant
• Sophisticated Power Management and OnNow/ACPI Unit
• Normal, doze, sleep, suspend and conserve modesSystem event monitoring with two event classesOne idle timer, one peripheral timer and one general purpose timerMore than ten general purpose input/output portsSix external event input ports with programmable SMI conditionComplete leakage control when external component is in power off statePrimary and secondary interrupt differentiation for individual channelsClock stretching, clock throttling and clock stop controlMultiple internal and external SMI sources for flexible power management modelsTwo programmable output portsAPM 1.2 compliantExtension to OnNow and ACPI (Advanced Configuration and Power Interface) support
• PCI to ISA Bridge
• Integrated 82C206 peripheral controllerIntegrated keyboard controller with PS2 mouse supportsIntegrated DS12885 style real time clock with extended 128 Byte CMOS RAMIntegrated USB (universal serial bus) controller with hub and two function portsIntegrated master mode enhanced IDE controller with enhanced PCI bus commandsPCI-2.1 compliant with delay transactionFour doubleword line buffer between PCI and ISA busSupports type F DMA transfersFast reset and Gate A20 operationEdge trigger or level sensitive interruptFlash EPROM, 2 MB EPROM and combined BIOS support
• Built-in nand-tree pin scan test capability
• 0.6um mixed voltage, high speed and low power CMOS process
• 208 pin PQFP for VT82C585VP
• 208 pin PQFP for VT82C586
• 100 pin PQFP for VT82C587VP