AMD's Bulldozer: More Design Details Surface

AMD has released new documents outlining the architecture for its upcoming Bulldozer release.

AMD's Bulldozer is one of the most highly-anticipated CPU architectures in recent memory. For those who are eager for more info on this new processor design, some new slides outlining Zambezi for the Socket AM3+ platform recently surfaced.

Breaking down the eight-core "Bulldozer" die, we find four modules that are each composed of two cores. Each module packs 2 MB L2 cache for a total of 8 MB. The is also an integrated Northbridge that contains 8 MB of L3 cache, two 72-bit DDR3 memory channels and four 16-bit receive/16-bit transmit HyperTransport links.

From the slides, we also see how Turbo Core will behave in Bulldozer. When the CPU's workload is within the TDP headroom, there is no core boost activity. When there is TDP headroom in given a workload, the Turbo Core kicks in and increases clock speed across the board. Conversely, when there is a lightly threaded workload, half the modules go into C6 sleep state, and the remaining cores get clocked up higher for better performance.

See the full deck of slides at Computerbase.