AMD Zen 6 'Venice' ES chips break cover with up to 192 cores, 32 per CCD, in early stress test — Kenya, Congo, Nigeria platforms leaked

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One of Zen 6's biggest upgrades is the larger core count CCDs for the Zen 6 and Zen 6c cores.

EPYC Turin
(Image credit: AMD)

Engineering samples of AMD's upcoming EPYC Zen 6 datacenter CPUs, codenamed Venice, have cropped up online. Uncovered by Olrak29_ on X, six different test results were published on OpenBenchmark.org, including some CPU specifications.

Sample 100-000001056-09 was tested on the Kenya platform featuring 128 cores, four CCDs, and two IODs. Lastly, three samples were tested on the Nigeria platform featuring two CPUs per setup. Sample 100-0002138-02 featuring 64 cores, two CCDs, two IODs, sample 100-000001056-03 featuring 128 cores, four CCDs, two IODs, and sample 100-000001051-08 featuring 192 cores with eight CCDs and two IODs.

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The CCD count of all the aforementioned samples reveals that these chips use likely use Zen 6c cores and come with higher-density CCDs compared to Zen 5. The 64-core and 128-core models come with 32 cores per CCD, while the 192-core trims use 24 cores per CCD. These numbers back up previous reports of Zen 6 improving the number of cores available on each CCD. AMD has yet to detail Zen 6 CCDs, but rumors suggest they'll come with up to 12 Zen 6 cores. Regardless, there's a high likelihood that space-optimized Zen 6c cores are at play here.

Unfortunately, some of the Openbenchmark listings are no longer available, but we were able to get clock speeds for one of the 64-core chips, which peaked at 3.54GHz.

Zen 6 is AMD's next-generation CPU architecture set to release in 2027, featuring up to 256 cores for the flagship datacenter parts. Venice will run on AMD's upcoming SP7 socket and feature significant improvements to memory bandwidth compared to Turin. One of the architecture's highlights is the jump in core count for both Zen 6 and Zen 6c. Zen 6 cores will reportedly be housed in 12-core CCDs, and Zen 6c cores will be housed in 32-core CCDs, respectively. AMD is also allegedly boosting L3 cache capacity to 48MB for Zen as well.

We've yet to hear any official news about Zen 6 in consumer platforms, codenamed Olympic Ridge. In generations past, AMD would introduce its consumer range before turning its attention to the data center. However, the company has only committed to a 2026 release for Venice, not for Olympic Ridge, so we could see the Epyc chips first as AMD tries to capitalize on renewed data center demand.

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Aaron Klotz
Aaron Klotz
Contributing Writer

Aaron Klotz is a contributing writer for Tom’s Hardware, covering news related to computer hardware such as CPUs, and graphics cards.

11 Comments Comment from the forums
  • alan.campbell99
    Coming to datacentre first and as yet no info on the consumer parts? Guess that shouldn't be a surprise right now.
    Reply
  • usertests
    Should be 8x 32-core Zen 6c CCDs disabled to 24 each. I doubt there will be any chiplet between 12 and 32 cores.

    I'm thinking the 32-core will have two ununified core complexes of 16 cores each and half of whatever amount of L3 is expected.
    Reply
  • wussupi83
    I want cheaper Threadrippers. Thanks.
    Reply
  • Findecanor
    How can a processor with 192 cores not be severely limited by memory bandwidth?
    Reply
  • Stomx
    Findecanor said:
    How can a processor with 192 cores not be severely limited by memory bandwidth?
    Yea, even 128-core Zen5 Turin is already limited in bandwidth, scales not that great with the number of cores versus smaller core number Genoa if you use slower speed DDR5-4800 from Genoa (and that is 4800*8bytes*12channels*1.e6 = 461 GB/s per socket). My tasks happen are very sensitive to the number of memory channels. If you move from using 6 to 8 and then to 12 memory channels the speed increases 20 and 18% or almost 40% in total

    But they plan to
    1) double memory speed from current Turin DDR5-6400, Venice Congo DDR5-8000 to the future Venice DDR5-12800,
    2) increase memory channels from 12 to 16

    Total will be 12800 * 8 * 16 * 1.e6 = 1.6 TB/s.
    Not bad

    All together with increase in inter-processor communication speed, getting more IPC on the 12-core CCD vs 8-core on Turin P and of course a bit higher clock frequency (with definitely higher TDP on a new socket), PCIe 6, should bring claimed 70% boost in benchmarks. Also not bad.

    Bad is that this memory will cost us @#$%^&* of money
    Reply
  • Dntknwitall
    alan.campbell99 said:
    Coming to datacentre first and as yet no info on the consumer parts? Guess that shouldn't be a surprise right now.
    This is they way it has always been done, this is nothing new and is expected.
    Reply
  • jp7189
    wussupi83 said:
    I want cheaper Threadrippers. Thanks.
    If you're willing to go used, EPYC platforms on ebay are way cheaper and way more performant than Threadripper.
    Reply
  • usertests
    jp7189 said:
    If you're willing to go used, EPYC platforms on ebay are way cheaper and way more performant than Threadripper.
    Can you give a good example + current pricing?

    I ask because it can be hard to figure out what's good on ebay since there are so many hundreds of options. For example, i7-10700 systems specifically may be flooding the market right now and how would you know?
    Reply
  • wussupi83
    jp7189 said:
    If you're willing to go used, EPYC platforms on ebay are way cheaper and way more performant than Threadripper.
    Hmm I'll have to check this out. I have a 9950x already, can I realistically get much better multi-core at around the same or better core component cost?
    Reply
  • wussupi83
    Findecanor said:
    How can a processor with 192 cores not be severely limited by memory bandwidth?
    I have many-core use cases that are not memory intensive. Wouldn't be much of a problem for me.
    Reply