Intel has chosen a fairly out-of-the-ordinary organization for the Atom, but without sacrificing performance (which is important with a CPU using an in-order architecture).
24 kB + 32 kB: An Asymmetrical Cache
The Atom’s Level-1 cache is 56 kB total: 24 kB for data and 32 kB for instructions. This asymmetry, fairly surprising for Intel, stems from the structure of the cache. Intel uses 8 transistors to store one bit, compared to six transistors in a standard cache. This technique allows the voltage applied to the cache to maintain information to be reduced. It seems that this move to 8-transistor cells was made late in the game, when the design of the processor was fairly advanced, which meant that the size of the cache had to be reduced to fit it in – which explains the 24 kB for the data cache. This unofficial explanation was advanced by AnandTech in their article introducing the Atom in April.
512 kB Level 2, shrinkable
The Level-2 cache has a capacity of 512 kB, and obviously runs at the same frequency as the processor. This 8-way cache is fairly classic and is close in performance to the one used in the Core 2 Duo (its latency is 16 cycles, compared to 14 for the Core 2). One of the new functions can deactivate part of the cache automatically – if a program doesn’t require much cache memory, part of it can be shut down. In practice, the cache goes from 8-way to 2-way (thus from 512 kB to 128 usable kB). This technique is a way of shaving a few precious milliwatts.
The FSB: Two modes of operation
The Atom’s FSB is the same one used by Intel since the Pentium 4. It operates in Quad Pumped (QDR) mode with GTL signaling. An interesting point: The Atom uses another signaling technology – CMOS mode. GTL is effective (the bus can reach 1,600 MHz), but power-intensive, whereas CMOS allows the bus voltage to be reduced. Technically, GTL uses resistors to improve the quality of the signal, but they aren’t really necessary except at higher frequencies. With the Atom and its bus, limited to 533 MHz, it’s possible to change to CMOS mode – the resistors are deactivated and the bus voltage is reduced by half. At the moment, only the SCH chipset is capable of handling the FSB in CMOS mode.