Intel's Ivy Bridge CPU Die Layout Estimated

As discussed at the IEEE International Solid-State Circuits Conference, Intel engineer Scott Siers announced that there will be four different Ivy Bridge die models. In addition, Ivy Bridge will carry up to 1.4 billion transistors that span over an area of 160 mm2, which is about 26 percent smaller than the comparable 216 mm2 Sandy Bridge die with 1.16 billion transistors. Ivy Bridge is built on 22 nm process, which is the "tick" process of Intel's Tick Tock Model.

Image Credit: Hiroshige GotoImage Credit: Hiroshige Goto

Taking a closer look at the Ivy Bridge's estimated die layout, the layout is similar in design to current-gen Sandy Bridge. The die is made up of three general sections, 1) CPU cores, 2) System Agent and 3) Graphics core.

The CPU cores are made up of four x86-64 cores with 256 KB dedicated L2 cache per core and shared 8 MB L3 cache. The System Agent holds the dual-channel DDR3 integrated memory controller (DDR3 1600), a PCIe interface (as a shared x16 port or two separate x8 ports), a DMI link, a display controller, power controller unit, and a FDI link. The Graphics Core has 16 programmable EUs that handle parallel processing loads for the GPU and can be programmed to perform GPGPU tasks. In addition, it holds the Multi-Format CODEC, which supports MPEG2, VC1, AVC and also MVC (multi-view video coding) for stereoscopic 3D. All the components are bound by a ring-bus that transports tagged data between the CPU cores, the graphics core, the L3 cache, and the system agent. 

Image Credit: Hiroshige GotoImage Credit: Hiroshige Goto

As Scott Siers announced, there will be four different variants of the Ivy Bridge die models.

  • 4+2: All four cores enabled, full 8 MB L3 cache enabled, all 16 shader cores (EUs) of the IGP enabled
  • 2+2: Two cores enabled, 4 MB L3 cache enabled, all 16 shader cores of the IGP enabled
  • 4+1: All four cores enabled, 6 MB L3 cache enabled, fewer shader cores of the IGP enabled
  • 2+1: Two cores enabled, 3 MB L3 cache enabled, fewer shader cores of the IGP enabled

   

Image Credit: Hiroshige GotoImage Credit: Hiroshige GotoImage Credit: Hiroshige GotoImage Credit: Hiroshige Goto

 

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  • hardcore_gamer
    1/3 rd of the die area is taken by the crappy GPU cores. They should have used it for additional logic or cache to speed up the CPU, atleast for the K series CPUs since the people who buy them use a discrete GPU anyway.
    23
  • killabanks
    memadmaxThe tick tock model is why intel will always be the innovator, and AMD the follower...

    more like billions of $$ means intel will always be ahead of amd
    20
  • fuzznarf
    hardcore_gamer1/3 rd of the die area is taken by the crappy GPU cores. They should have used it for additional logic or cache to speed up the CPU, atleast for the K series CPUs since the people who buy them use a discrete GPU anyway.

    Yeah, you're right. Intel probably has no idea what they are doing....
    11
  • Other Comments
  • ojas
    I wonder if they'd keep the die size the same as sandy bridge, wouldn't that let them stuff more things like cache and IGP shaders (or whatever IGPs have) in the same space?
    2
  • memadmax
    The tick tock model is why intel will always be the innovator, and AMD the follower...
    -10
  • hardcore_gamer
    1/3 rd of the die area is taken by the crappy GPU cores. They should have used it for additional logic or cache to speed up the CPU, atleast for the K series CPUs since the people who buy them use a discrete GPU anyway.
    23