The Conroe test system features a 2.66 GHz Conroe dual core processor with a 266 MHz Front Side Bus (FSB1066 at quad data rate). Each core has a 64 kB L1 cache, divided into a data cache and instruction cache of 32 kB each. The processor also includes a whopping 4 MB of L2 Cache, shared by the cores.
The Conroe processor is clocked at 2.66 MHz, and is built using Intel's latest 65 nm process technology.
Previous generations of dual core processors from both Intel and AMD have consisted of two individual processors merged onto a single die or placed into a package. In both cases, these were tied together using an internal interconnect: Intel used the FSB, while AMD utilized Hyper Transport. Each of these CPU cores had its own dedicated L2 cache, and could only access the L2 cache of the other CPU core by going over this interconnect.
The Conroe architecture departs from these "separate but equal" designs by incorporating separate CPU processor cores that share a common L2 cache. Depending on the load on each processor core, portions of the cache are allocated to one or the other, using Intel's Advanced Smart Cache technology. If one single-threaded application runs on one of the cores - which is still the case of the majority of programs today - the active core is granted exclusive access to the entire 4 MB L2 cache. This is one reason why this processor is extraordinarily fast if you do a clock-to-clock comparison with the Pentium D. When two applications run in tandem, where one application only requires a small amount of cache space to run, the other program can grab the entire remaining L2 cache space for its own use. Intel had already made clear that it could manage shared cache in this way with the introduction of its Core Duo mobile processors (code-named Yonah).