- Support Host bus and memory bus frequency up to 83.3 MHz.
- Meet PC97 Requirements
- Integrated Second Level ( L2 ) Cache Controller
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- Write Back Cache Modes
- Support WBINVD flush L2 Cache for AGP
- Integrated 32K bits Dirty RAM
- 32 kbit Invalid RAM
- Support Pipelined Burst SRAM
- Support 256k/512k/1M Cache Sizes
- Integrated DRAM Controller
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- Support 6 RAS Lines for FPM/EDO/SDRAM DIMMs/SIMMs
- Support 2 MBytes to 768 MBytes of main memory
- Support 256k/512K/1M/2M/4M/8M/16M/32M x N FPM/EDO/SDRAM/DRAM
- Support 3.3V or 5V DRAM
- Support FPM DRAM 5/6-3-3-3(-3-3-3-3) Burst Read Cycles
- Support EDO DRAM 5/6-2-2-2(-2-2-2-2) Burst Read Cycles
- Support SDRAM 5/6/7/8-1-1-1(-2-1-1-1) Burst Read Cycles
- Support X-1-1-1/X-2-2-2/X-3-3-3 Burst Write Cycles
- Support 8 Qword Deep Buffer for Read/Write Recordering, Dword Merging and 3-1-1-1 Post write Cycles
- Provides High Performance PCI Arbiter
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- Support up to 5 external PCI Masters
- Support Concurrency between CPU/L2 and AGP/Memory
- Support Concurrency between CPU to Memory and PCI to PCI
- Integrated Host-to-PCI Bridge
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- Support Asynchronous and Synchronous PCI Clock
- Support IDE Posted Write
- Support Pipelined Process in CPU-to-PCI Access
- Support Advance Snooping for PCI Master Bursting
- Integrated A.G.P Compliant Target/66 MHz Host-to-PCI Bridge
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- Programmable counters to Ensure Guaranteed Minimum access time for low priority request, CPU to AGP and AGP Master transactions.
- Support Pipelined Process in CPU-to-A.G.P. Access
- Support Advance Snooping for A.G.P Master initiate system memory accesses with PCI cycles.
- Support 8 Way, 16 Entries GRLT(Graphics Remapping Lookaside Table) to enhance A.G.P. Read/Write Performance
- Support PCI-to-PCI bridge function for memory write from 33 MHz PCI bus to A.G.P bus
- Integrate Posted Write Buffers and Read Prefresh Buffers to Increase System Performance
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- CPU-to-Memory Posted Write Buffer (CTMFF) with 8 QW Deep
- CPU-to-Memory Read Buffer with 4 QW Deep
- CPU-to-PCI Posted Write Buffer(CTPFF) with 8 QW Deep
- PCI-to-Memory Posted Write Buffer(CTPFF) with 8 QW Deep
- PCI-to-Memory Read Prefresh Buffer(CTPFF) with 8 QW Deep
- CPU-to-PCI66 Posted Write Buffer(CTAFF) with 8 QW Deep
- PCI66-to-Memory Posted Write Buffer(CTAFF) with 8 QW Deep
- Request queue with the depth of 32
- High/low priority write queue with 64 QW Deep
- High/low priority read return queue with 64 QW Deep
- Embeded KBC/RTC/USB
- Embeded Data Acquisition Logic
- Support Common Architecture
- Support Ultra DMA 33
- Support Keyboard Power On System Function
- Support I2C Serial Bus
- Support 2 MB Flash ROM Interface
- 5591 : 533 Balls BGA Package and 0.35um 3.3V Technology
- 5595 : 208 PQFP Package and 0.5 um 5V Technology
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Summary
- Overview
- Slot 1 AGP Chipsets
- Intel 440BX AGP Chipset - 66/100 MHz Front Side Bus
- Aladdin Pro II / M1621/ M15X3 AGP Chipset - 66/100 MHz Front Side Bus
- Intel 440LX AGP Chipset - 66 MHz Front Side Bus
- Intel 440EX AGP Chipset - 66 MHz Front Side Bus
- ALI Aladdin V AGP Chipset - 66/100 MHz Front Side Bus
- VIA Apollo MVP3 AGP Chipset 66/100 MHz Front Side Bus
- SiS 5591/92 AGP Chipset - 66/75/83 MHz Front Side Bus
- VIA Apollo VP3 AGP Chipset - 66 MHz Front Side Bus
- ALI Aladdin IV+ Chipset - 66/75/83 MHz Front Side Bus
- SiS 5581/82 AGP Chipset - 66/75 MHz Front Side Bus
- SiS 5597/98 Chipset - 66/75 MHz Front Side Bus
- VIA Apollo VP2 Chipset - 66/75 MHz Front Side Bus
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