First used in the P6 (or sixth-generation) processors, dynamic execution enables the processor to execute more instructions in parallel, so tasks are completed more quickly. This technology innovation is composed of three main elements:
- Multiple branch prediction—Predicts the flow of the program through several branches
- Dataflow analysis—Schedules instructions to be executed when ready, independent of their order in the original program
- Speculative execution—Increases the rate of execution by looking ahead of the program counter and executing instructions that are likely to be necessary
Branch prediction is a feature formerly found only in high-end mainframe processors. It enables the processor to keep the instruction pipeline full while running at a high rate of speed. A special fetch/decode unit in the processor uses a highly optimized branch-prediction algorithm to predict the direction and outcome of the instructions being executed through multiple levels of branches, calls, and returns. It is similar to a chess player working out multiple strategies in advance of game play by predicting the opponent’s strategy several moves into the future. By predicting the instruction outcome in advance, the instructions can be executed with no waiting.
Dataflow analysis studies the flow of data through the processor to detect any opportunities for out-of-order instruction execution. A special dispatch/execute unit in the processor monitors many instructions and can execute these instructions in an order that optimizes the use of the multiple superscalar execution units. The resulting out-of-order execution of instructions can keep the execution units busy even when cache misses and other data-dependent instructions might otherwise hold things up.
Speculative execution is the processor’s capability to execute instructions in advance of the actual program counter. The processor’s dispatch/execute unit uses dataflow analysis to execute all available instructions in the instruction pool and store the results in temporary registers. A retirement unit then searches the instruction pool for completed instructions that are no longer data dependent on other instructions to run or which have unresolved branch predictions. If any such completed instructions are found, the retirement unit or the appropriate standard Intel architecture commits the results to memory in the order they were originally issued. They are then retired from the pool.
Dynamic execution essentially removes the constraint and dependency on linear instruction sequencing. By promoting out-of-order instruction execution, it can keep the instruction units working rather than waiting for data from memory. Even though instructions can be predicted and executed out of order, the results are committed in the original order so they don’t disrupt or change program flow. This enables the P6 to run existing Intel architecture software exactly as the P5 (Pentium) and previous processors did—just a whole lot more quickly!
- Processor Features, Explored
- Superscalar Execution
- MMX Technology: SSE And 3DNow!
- Dynamic Execution
- Dual Independant Bus Architecture
- Hyper-Threading Technology
- Multi-Core Technology
- Hardware-Assisted Virtualization Support
- Processor Socket And Slot Types
- Intel Sockets: LGA 775, LGA 1156, LGA 1366, And LGA 1155
- AMD Sockets: AM2/AM2+/AM3/AM3 And F/FM1/FM2
- CPU Operating Voltages And Math Coprocessors (Floating-Point Units)
- Processor Bugs And Steppings
- Intel Core ix-Series And Atom Processors
- AMD K10, Bulldozer, Piledriver CPUs, And Fusion/HSA APUs