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RAM Wars: Return of the JEDEC

Enter GDDR2 SDRAM

Why are graphics heavyweights ATI and Nvidia jumping ahead of everyone else, including JEDEC, with their own proprietary versions of DDRII? Because as the GPU has gained ground in the PC performance hierarchy, so have the requirements of SGRAM memory, or video memory.

Indeed, the graphics processor world has seen many great advances during the past few years - many a result of the slugfest between ATI and Nvidia to offer the best graphics card capable of matching the best games out there (anyone who has played Halo or Unreal with a Radeon or GeForce video card online late past midnight, only to call in sick at work or skip school the next day, knows this). In many respects, after a certain clock-speed threshold has been reached, the distinguishing factors of the GPU have become more crucial for graphics performance; and, in order to match the GPU's processing capabilities, ultra-high performance memory must be on the menu as well.

Micron is well aware of this, and along with Samsung and Hynix, has begun developing graphics DDRII memory prior to the finalization of a graphics DDRII standard by JEDEC, which is slated for this summer. This memory, now known as GDDR2, will do a lot to accommodate the powers of ATI's latest Radeon and Nvidia's GeForceFX, as well as other vendors' goods, such the latest devices from Trident or S3 with 1 GHz of bandwidth.

DDR's double-fetch-per-cycle capability for graphics has helped, but in a recent patent filing Micron has indicated that a burst operation is required, which Micron defines as an operation retrieving a given number of data stored at sequential locations within the memory.

Additionally, GDDR2 will include a memory array that is addressable by even and odd word addresses. The logic circuitry with a burst increment mode will access the array starting at an even word address, and a burst decrement mode will access the array starting at an odd word address.

Within the scope of Micron's burst mode, the memory device has a burst increment mode when starting at an even word address, and a burst decrement mode when starting at an odd word address. Data increments are counted, so that the second data word retrieved is still from the same memory location as the first data word as addressed by the logic circuitry. When starting at an odd word address, the device counts down (decrements), so that the second data word retrieved is still from the same memory location as the first data word as addressed by the logic circuitry.

But, as if GDDR2 were not enough for the GPU when it now looks as if DDRII for CPU chipsets may not see wide-scale application before 2005, Micron, Infineon, Elpida, and Hynix says they will have samples of GDDR3 this year.