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Toshiba Sampling 64GB UFS-Based NAND chips

By - Source: Toshiba | B 12 comments

Toshiba is now shipping 64 GB NAND flash modules using the UFS interface.

Toshiba said last week that it began sampling out new 64 GB embedded NAND flash memory modules packed with a UFS interface (I/F). Designed for a wide range of small form factor products like smartphones and tablets, the new module is fully compliant with the JEDEC UFS v1.1 standard and supports the use of "lanes".

"The JEDEC UFS Ver.1.1 compliant interface handles essential functions, including writing block management, error correction and driver software," Toshiba said. "It simplifies system development, allowing manufacturers to minimize development costs and speed up time to market for new and upgraded products."

The company said the new modules are sealed in a small FBGA package measuring a mere 12- x 16- x 1.2-mm and uses 169 balls. Voltage ranges from 2.7V to 3.6V for the memory core, 1.7V to 1.95V for the controller core, and 1.10V to 1.30V for the UFS interface signals.

The UFS serial interface has scalability the in number of lanes and speed. Toshiba's new modules offer single upstream and downstream lanes with 2.9 Gbit/sec bandwidth. Samples now shipping are mainly intended for evaluation of the UFS interface and its protocol in host chipsets and by OS vendors.

"Demand continues to grow for large density, high-performance chips that support high resolution video, driven by improved data-processing speeds in host chipsets and wider bandwidths for wireless connectivity," the company said. "Toshiba has proved itself an innovator in this key area, and is now reinforcing its leadership by being first in the industry to support samples with a 64GB UFS module."

Commercialization will depend on how receptive OEMs will be with these new chips using the UFS standard, so stay tuned.

 

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  • 4 Hide
    saturnus , February 12, 2013 8:28 AM
    UFS, or in laymans terms USB gone SCSI, is a very interesting technology for mobile devices that could over time make actual separate volatile memory redundant as the transfer rates using only a single lane offer half the transfer rate as current LPDDR2 memory. One could easily imagine that with several lanes to each module and more modules in parallel could replace the need for DRAM in mobile devices altogether.
  • 0 Hide
    master_chen , February 12, 2013 8:37 AM
    Why do I feel like "Rambus 2.0"?
  • 0 Hide
    ojas , February 12, 2013 9:23 AM
    saturnusUFS, or in laymans terms USB gone SCSI, is a very interesting technology for mobile devices that could over time make actual separate volatile memory redundant as the transfer rates using only a single lane offer half the transfer rate as current LPDDR2 memory. One could easily imagine that with several lanes to each module and more modules in parallel could replace the need for DRAM in mobile devices altogether.

    Give it 5 years and Intel will integrate this into their CPUs... :lol: 

    But actually...if what you're saying is correct...it would be kind of cool, to have one of these as an expansion card to your mobile devices. Increase RAM and storage simultaneously.
  • 0 Hide
    icemunk , February 12, 2013 10:30 AM
    heh. 169 balls. :p 
  • 2 Hide
    shriganesh , February 12, 2013 10:58 AM
    169 balls.........! Wow! That's a lot of balls for a tiny chip :D 
  • 1 Hide
    josejones , February 12, 2013 11:50 AM
    The article discusses "64 GB embedded NAND flash memory modules" but doesn't explain what the previous specs were so, how are us noobs suppose to know what the upgrade really is when the article doesn't give us the last model specs to compare it to?
  • 0 Hide
    master_chen , February 12, 2013 2:31 PM
    Quote:
    169 balls.........! Wow! That's a lot of balls for a tiny chip :D 

    Those balls are still "small balls"...geddit?
  • 0 Hide
    richwaa , February 12, 2013 2:45 PM
    @saturnus: Sorry to disagree with you about UFS eventually making the need for separate volatile RAM redundant; it will not. UFS is an evolved interface spec for flash memory and does nothing to eliminate the inherent limitations in the flash memory itself. The number of memory operations that occur with code execution would create inherent instabilities in the current flash technologies that we don't know how to overcome --- yet. Running flash modules in parallel, as you suggest, would greatly exacerbate the already known problems with flash technologies; there's are really good reasons why disk/flash access moved from parallel to serial access such as clocking, capacitance, etc.

    http://en.wikipedia.org/wiki/Flash_memory#Limitations
  • -2 Hide
    richwaa , February 12, 2013 2:45 PM
    @saturnus: Sorry to disagree with you about UFS eventually making the need for separate volatile RAM redundant; it will not. UFS is an evolved interface spec for flash memory and does nothing to eliminate the inherent limitations in the flash memory itself. The number of memory operations that occur with code execution would create inherent instabilities in the current flash technologies that we don't know how to overcome --- yet. Running flash modules in parallel, as you suggest, would greatly exacerbate the already known problems with flash technologies; there's are really good reasons why disk/flash access moved from parallel to serial access such as clocking, capacitance, etc.

    http://en.wikipedia.org/wiki/Flash_memory#Limitations
  • -2 Hide
    richwaa , February 12, 2013 2:45 PM
    @saturnus: Sorry to disagree with you about UFS eventually making the need for separate volatile RAM redundant; it will not. UFS is an evolved interface spec for flash memory and does nothing to eliminate the inherent limitations in the flash memory itself. The number of memory operations that occur with code execution would create inherent instabilities in the current flash technologies that we don't know how to overcome --- yet. Running flash modules in parallel, as you suggest, would greatly exacerbate the already known problems with flash technologies; there's are really good reasons why disk/flash access moved from parallel to serial access such as clocking, capacitance, etc.

    http://en.wikipedia.org/wiki/Flash_memory#Limitations
  • 1 Hide
    didgetmaster , February 12, 2013 4:00 PM
    Why is it so difficult to detect and eliminate duplicate comment submissions?

    Why is it so difficult to detect and eliminate duplicate comment submissions?

    Why is it so difficult to detect and eliminate duplicate comment submissions?
  • 0 Hide
    blazorthon , February 13, 2013 3:06 AM
    richwaa@saturnus: Sorry to disagree with you about UFS eventually making the need for separate volatile RAM redundant; it will not. UFS is an evolved interface spec for flash memory and does nothing to eliminate the inherent limitations in the flash memory itself. The number of memory operations that occur with code execution would create inherent instabilities in the current flash technologies that we don't know how to overcome --- yet. Running flash modules in parallel, as you suggest, would greatly exacerbate the already known problems with flash technologies; there's are really good reasons why disk/flash access moved from parallel to serial access such as clocking, capacitance, etc.http://en.wikipedia.org/wiki/Flash_memory#Limitations


    Well, they could do something more like PCIe with multiple serial lanes, granted I still wouldn't want flash memory to replace DRAM. Flash's increasingly poor endurance with every process shrink and bits per cell increase would probably only help planned obsolescence supporters.

    saturnusUFS, or in laymans terms USB gone SCSI, is a very interesting technology for mobile devices that could over time make actual separate volatile memory redundant as the transfer rates using only a single lane offer half the transfer rate as current LPDDR2 memory. One could easily imagine that with several lanes to each module and more modules in parallel could replace the need for DRAM in mobile devices altogether.


    Many SoCs have memory bandwidth in several GB/s. Going down to a few Gb/s is a huge downgrade in performance. No, these memory chips are not half the transfer rate of current LPDDR2 memory. As is, memory bandwidth of mobile devices is often one of the greatest bottle-necks for performance, so such a step back or even going with what I said above to maybe get similar performance is not the trend that is needed right now.