PCI-SIG Talks PCIe 4.0 at Its Developers Conference

Featured speakers at this week's PCI-SIG developer conference included Al Yanes, President and Chairman, and Ramin Neshati, Serial Communications Workgroup Chair. Discussion included talk of PCI Express (PCIe) and new updates to meet the evolving demands of a variety of computing markets from high-performance storage to ultra-thin and light mobile devices. Increased performance and new form factors frame the organization's focus as it delivers new technologies built upon the 20-year legacy of the Peripheral Component Interface (PCI).

This year marks 10 years of PCIe press specification development and PCI-SIG is now turning its focus to driving I/O technology forward through advancements in PCIe-attached storage, new form factors and performance enhancements for the PCIe specification.

In June of 2011, we learned for the first time about the upcoming PCIe 4.0, even before PCIe 3.0 hit the market. PCIe 4.0 technology is being developed to deliver 16GT/s, doubling the bandwidth over the PCIe 3.0 specification with seamless backward compatibility to all previous versions of PCIe technology. The PCIe 4.0 architecture is designed to double the data rate, while maintaining its position as a low-cost, high performance I/O technology. With the increase in clock rate designers can implement narrower links, thereby saving cost through pin reduction. The final PCIe 4.0 specifications, including form factor specification updates, are expected to be available in late 2015.

In late 2011, we saw the first wide spread implementation of the PCIe 3.0 standard in the market. With implementation of PCIe 3.0, PCIe-attached storage can achieve significantly higher bandwidth using processor-integrated PCIe 3.0 technology that is directly attached to storage sub-systems. As we discussed in 2010, PCIe 3.0 offers double the bandwidth over previous generation PCIe 2.0.

"PCI Express 2.0 uses an 8b/10b encoding scheme, where 8 bits of data are mapped to 10-bit symbols to achieve DC balance. The result is 20% overhead, cutting effective bit rate. PCI Express 3.0 moves to a much more efficient 128b/130b encoding scheme, eliminating the 20% overhead. So, the 8 GT/s won’t be a “theoretical” speed; it will be the actual bit rate, comparable in performance to 10 GT/s signaling with 8b/10b."

The PCIe 3.0 standard is optimized for high performance solid-state drives (SSDs) in enterprise and client applications, and is well-positioned to address growing demands for increased storage I/O speeds.

PCI-SIG also provided some insight on new form factors, which include the PCIe OCuLink, NGFF and SFF electrial specifications.

  • PCIe OCuLink, a small cable form factor supporting optical and copper optimized for internal and external enclosure usage, is being designed to offer bit rates starting at 8Gbps, with headroom to scale, and new independent cable clock integration. The internal and external connector supports up to four PCIe lanes, with all cables supporting 8GT/s. This provides up to 32Gbps in each direction within a four lane configuration; one lane and two lane configurations are also supported.
  • Next generation form factor that will be part of the Mini CEM specification is being designed for the emerging ultra-light and thin platforms. A natural transition from the existing Mini CEM specification, this form factor is more flexible, smaller in both size and volume, offers better scalability and supports multiple technologies including Wi-Fi®, SSD and wireless wide area network (WWAN).
  • The development of an electrical specification for the SFF-8639 connector which is intended for use in the growing PCIe-attached storage market.

"Each new technical innovation is a testament to the importance of PCI-SIG, providing our membership and the computing industry with future-focused technology, ensuring that increased performance is among one of our top priorities," said Al Yanes, PCI-SIG president and chairman. "We plan to celebrate 20 years of innovation by continuing to seek new ways to deliver PCIe technology across a variety of computing platforms."

"The PCI-SIG has amassed a long-term record of technical innovation tempered by real-world requirements for backward compatibility," said Bob Wheeler, senior analyst at The Linley Group. "PCIe 4.0 is poised to continue this market-savvy approach while keeping the technology on the leading edge of economical interconnects."

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    Top Comments
  • rocknrollz
    Its like putting a car on a 200mph race track when it can only do 100.


    Exactly, but what happens when we get the tech to go up to the track? Then we gotta rebuild it all. Better to have it available now, then later.
    13
  • Anonymous
    It's not all about graphics cards. PCIe SSD's will need the bandwidth to keep pushing I/O.
    12
  • Other Comments
  • loops
    I just need to find a GPU that will fill the lanes.
    2
  • Pinhedd
    loopsI just need to find a GPU that will fill the lanes.


    Graphics cards may be the most popular PCIe add-in cards but many onboard devices also communicate with the chipset or CPU by PCIe. Onboard peripherals that are added by the motherboard manufacturer such as audio, ethernet, USB 3.0, extra SATA ports, bluetooth, wifi, etc... are often wired up using PCIe links. Newer PCIe generations will allow these devices to provide greater services without increasing the complexity of the motherboard.
    8
  • the3dsgeek
    i don't know where are they going with this, today's graphic cards performs the same in the old generation PCIe slots, or i don't know, maybe 2-3% difference. First make the hardware that can take advantage of the available bandwidth. Its like putting a car on a 200mph race track when it can only do 100.
    -15