Intel Reveals More Details of Ivy Bridge Variants at ISSCC
Intel has revealed further details about its 22nm Ivy Bridge platform at the IEEE International Solid-State Circuits Conference, which currently takes place in San Francisco.
Following the initial disclosure of Ivy Bridge at IDF Fall 2011, Intel engineer Scott Siers announced that there will be four different Ivy Bridge die models. The dies will integrate two or four cores, two different DX11 graphics units, as well 2 to 8 MB L3 cache. Ivy Bridge will carry up to 1.4 billion transistors that span over an area of 160 mm2, which is about 26 percent smaller than the comparable 216 mm2 Sandy Bridge die with 1.16 billion transistors.
Ivy Bridge will also integrate DisplayPort support and 20 channels of PCIe 3. The memory controller now supports 1.35V DDR3L SODIMMs.
Digitimes reported last week that Ivy Bridge would not be shipping as planned, as the production of the processors appears to be delayed. According to the publication, a small volume of Ivy Bridge chips will be available in April with volume shipments not happening until Q3, which would mean - if Digitimes is right - that volume Ivy Bridge computers won't be available until early Q4. The culprit apparently is the economy and weak demand, which makes it difficult for PC makers to get rid of their Sandy Bridge inventory. However, Intel told VR-Zone that the report is only partially true and only dual-core Ivy Bridge models will be delayed.