Intel Nova Lake die sizes leak, signaling higher cost — smaller compute tile still demands higher price on TSMC N2
But that is with bLLC.
Intel expects its Core Ultra series 4 processors, codenamed Nova Lake, to change its fortunes on the desktop and laptop markets and finally offer performance that is higher compared to direct competitors from AMD. However, another important factor to consider will be the costs of these CPUs, and if the alleged Nova Lake compute chiplet die sizes leaked by @9550pro are accurate, these processors will be anything but cheap to make.
When implemented on TSMC's N2 manufacturing technology, Nova Lake's compute tile with eight high-performance Coyote Cove P-cores and 32 energy-efficient Arctic Wolf E-cores measures over 110 mm^2, whereas the same tile equipped with 144 MB of big last-level cache (bLLC) measures over 150 mm^2, if the numbers from @9550pro are correct. To put the number into context, it is believed that the size of Arrow Lake's compute tile —implemented on TSMC's N3B technology and housing eight Lion Cove P-cores and 16 Skymont E-cores — is believed to be around 117 mm^2.
TSMC's N2 is projected to be a more expensive process technology to use than N3B, as, despite the fact that it is expected to feature roughly the same number of EUV layers (20 ~ 23), it is also believed to use EUV multipatterning for at least some critical layers, which adds costs. This, and other factors, contribute to manufacturing costs, so it is safe to say that Nova Lake's compute tile without bLLC will be a bit more expensive to make than Arrow Lake's compute tile, assuming an accurate die size for the former. The compute tile with bLLC will be significantly more expensive, though, considering that these tiles will be used for expensive CPUs aimed at gamers and enthusiasts, this will hardly be a problem for Intel.
Just like most of Intel's latest processors in recent years, Nova Lake will use a multi-tile design that will include a compute tile (or two), a system-on-chip (SoC) tile, a GPU tile, an I/O tile, and a base tile. The main chiplet — the compute tile — will be made using both Intel's own 18A fabrication technology at the company's Fab 32 in Arizona as well as TSMC's N2 manufacturing process at the foundry's Fab 22 in Taiwan.
Intel has never publicly revealed which versions of Nova Lake will be used for desktops and which will be used for laptops, and whether there will be any difference at all. However, given that Intel expects to make the majority of Nova Lake silicon in-house and keeping in mind that laptop CPUs outsell desktop CPUs 7:3 these days, it is reasonable to expect that the bulk of laptop CPUs will be made at Intel's own fab in Arizona. To that end, the company's balance sheet will barely suffer from the high costs of its Nova Lake compute tiles with bLLC at TSMC.
The cost of a chip is a function of process technology, die size, functional yield, and parametric yield. While we may well speculate that TSMC's N2 is more expensive than N3B, without factors like parametric yields, our assumptions about the costs of the actual compute tile will be highly speculative, to put it mildly.
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Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.
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rluker5 Compute tile made at both fabs, interesting.Reply
If 18a is used for mobile, maybe next year there will be an Erying mobo with one and maybe they could be compared on a.more apples to apples basis. -
bit_user Reply
The Zen 6 CCD is rumored to be just 76 mm², on TSMC N2, featuring 12 big cores (source: https://www.techpowerup.com/345839/amd-zen-6-ccd-packs-12-cores-48-mb-l3-cache ). That doesn't surprise me, given that Zen cores have always been a little bit narrower than competing Intel P-cores and Intel's E-cores are starting to get rather large.The article said:When implemented on TSMC's N2 manufacturing technology, Nova Lake's compute tile with eight high-performance Coyote Cove P-cores and 32 energy-efficient Arctic Wolf E-cores measures over 110 mm² -
thestryker Given that Jaykihn's estimate was ~94 mm² this is a pretty significant difference. Makes me wonder if we're talking manufacturing node differences or if one of them is just wrong.Reply -
JRStern Reply
Could it be cold silicon? Spread the circuitry out a little for heat management? Then you might get a big tile with the (better) yield of a smaller tile. You waste a little silicon but that's almost trivial in the complete process.thestryker said:Given that Jaykihn's estimate was ~94 mm² this is a pretty significant difference. Makes me wonder if we're talking manufacturing node differences or if one of them is just wrong. -
bit_user Reply
That might influence the layout of cores vs. cache, but there's no chance it's going to actually have just dark silicon.JRStern said:Could it be cold silicon? Spread the circuitry out a little for heat management? -
palladin9479 Why so many e cores? All that does is win synthetic benchmarks but, as demonstrated by AMD x3d models, it won't drive much else. 8 p cores are 4-8 e cores are more then sufficient for any consumer compute task. Anything benefiting from more slow e cores would be better run on a dGPU with thousands of such cores.Reply -
bit_user Reply
The E-cores in my Alder Lake i9 development machine definitely improve compile times on large software projects, which is the main thing I use it for. I've played around with using taskset to restrict compilation to different groups of cores, and the E-cores easily pull their weight!palladin9479 said:Why so many e cores? All that does is win synthetic benchmarks but, as demonstrated by AMD x3d models, it won't drive much else.
In fact, I wanted to do a CPU upgrade to Raptor Lake, mainly just to get more E-cores. Sadly, it's a Dell and its BIOS won't allow a CPU upgrade on that motherboard. Somebody actually tried it, and the BIOS refused to boot. I checked and I have the same motherboard revision as theirs. -
thestryker Reply
It's pretty simple: Intel is keeping their 8P/16E design Compute Tile design and they're not going to arbitrarily disable a bunch of E-cores when using two of them.palladin9479 said:Why so many e cores?
By this logic why does AMD have 16 core parts (let alone the very likely forthcoming 24 core)?palladin9479 said:All that does is win synthetic benchmarks but, as demonstrated by AMD x3d models, it won't drive much else.
In the case of these dual Compute Tile parts they seem likely aimed at people who do more production oriented things but don't need additional memory bandwidth or PCIe connectivity. A 52 core NVL part should be faster in MT than all but 2 of the workstation Xeon 6 parts launching this year and it'll be much faster than any of them in lighter and ST workloads. -
JRStern Reply
Wait and see, even if it's just a bit around the edges, maybe an island near dead center.bit_user said:That might influence the layout of cores vs. cache, but there's no chance it's going to actually have just dark silicon.