Page 1:Intel's Vision Of Future And What The Alderwood/Grantsdale Launch Is All About
Page 2:BTX Form Factor: More Efficient Layout For Components
Page 3:Volumetric Zones
Page 4:BTX, MicroBTX, PicoBTX
Page 5:Cooling The Core Components Via Thermal Module
Page 6:DDR2: 200 And 266 MHz To Start With
Page 7:DDR2 Latency Times
Page 8:Overview Of DDR Vs. DDR2
Page 9:A Quick Start: Corsair CM2X512
Page 10:PCI Express: Up To 8 GB/s
Page 11:PCI Express Graphics Cards
Page 12:PCI-X Vs. PCI Express
Page 13:Socket 775: CPUs Without Pins
Page 14:Comparison: Sockel 478 And Socket 775
Page 15:Prescott Vs. Northwood: An Insight
Page 16:Grantsdale/Alderwood In Detail
Page 17:Southbridge: ICH6, ICH6R, ICH6W
Page 18:MainConcept MPEG Encoder
Page 19:SiSoft Sandra Pro 2004
Page 20:The Competition: SiS And VIA
DDR2: 200 And 266 MHz To Start With
With DDR2, the contacts move closer together, since there are 240 pins, instead of 184.
As opposed to DDR memory, which was accelerated to more than 233 MHz by many manufacturers, a JEDEC specification has been in existence since September 12, 2003 for DDR2. This specification is meant to help prevent compatibility problems as much as possible, and this might be the case in practice, especially since there is enormous support for DDR2 in the IT industry and since DDR2 is viewed as the next phase in evolution from DDR memory.
DDR2 is based on the well-established Double Data Rate technology. This means that data is transferred with both the rising and falling flanks per clock cycle. Thus, clock rates of 200 MHz and 266 MHz translate to DDR2 400 and DDR2 533 in marketing-speak. The next levels would be DDR2 667 and DDR2 800, but these are not to be expected this year.
Among the new technical features of DDR2 are the new signal terminations directly on the memory (ODT - On Die Termination), reduced page sizes (requires less power for activation) and fixed burst lengths of four and eight cycles. In the case of the latter, the specification provides for a new burst type called Sequential Nibble, which divides the burst into two 4 bit Nibbles. This also enables burst lengths of eight cycles in interleaving mode because each new column of the memory matrix can still be used with the new 4 bit prefetch.
Posted CAS makes it possible to carry out a CAS command directly after the RAS signal without any collisions. This simplifies the design of the controller and increases the theoretical load that the memory can handle.
Further differences between DDR and DDR2 are found in the details: instead of the TSO (Thin Small Outline) packages, only the FBGA (Fine-Line Ball Grid Array) casing is used. In addition to shorter circuits and reduced signal noise, FBGA has the advantage of being much more compact in size, which allows for higher memory densities. Another difference is that DDR2 DIMMs work with 1.8 V instead of the 2.5 V of DDR - this minimizes loss in performance and enables higher clock rates in the mid-term.
In terms of width, a DDR1 module fits in the 240 pin DDR2 socket, but the position of the notch is different.
- Intel's Vision Of Future And What The Alderwood/Grantsdale Launch Is All About
- BTX Form Factor: More Efficient Layout For Components
- Volumetric Zones
- BTX, MicroBTX, PicoBTX
- Cooling The Core Components Via Thermal Module
- DDR2: 200 And 266 MHz To Start With
- DDR2 Latency Times
- Overview Of DDR Vs. DDR2
- A Quick Start: Corsair CM2X512
- PCI Express: Up To 8 GB/s
- PCI Express Graphics Cards
- PCI-X Vs. PCI Express
- Socket 775: CPUs Without Pins
- Comparison: Sockel 478 And Socket 775
- Prescott Vs. Northwood: An Insight
- Grantsdale/Alderwood In Detail
- Southbridge: ICH6, ICH6R, ICH6W
- MainConcept MPEG Encoder
- SiSoft Sandra Pro 2004
- The Competition: SiS And VIA