Source: Micron DesignLine Vol. 12, 3Q03

Source: Micron DesignLine Vol. 12, 3Q03

The illustrations show the latency times during the read process. However, the latency times during the write process have also changed: while conventional DDR memory can record data exactly one cycle after the actual write command, this could go awry with DDR2 due to the higher clock rates. Thus, the write latency is calculated by using the read latency minus one clock cycle.