Motherboard BIOS menus offer numerous settings to optimize your memory. These settings modify RAM functions that, while basic in nature, are often given widely different names. We'll briefly explain the options. The usual values are listed in brackets; the ideal setting is underlined. We've also included examples of what the settings might be called in different BIOS versions. Please note that not all BIOS menus offer all the settings.
Automatic Configuration (On/ Off )
(DRAM Auto, Timing Selectable, Timing Configuring) If you want to manually configure your memory timings, you will have to deactivate the automatic RAM configuration.
Bank Interleaving (Off/ 2/ 4 )
(Bank Interleave) DDR RAM memory chips are made of four banks. Addressing all four banks through interleaving at the same time will maximize your performance.
Burst Length (4/ 8 )
The burst length specifies how many data blocks are sent in one transmission cycle. Ideally, one transmission will fill one memory row on the L2 cache found in modern Pentium 4 and Athlon XP CPUs. That is equal to 64 Bytes, or eight data packets.
CAS Latency TCL (1.5/ 2.0 / 2.5/ 3.0)
(CAS Latency Time, CAS Timing Delay) The number of clock cycles that pass from the column being addressed to the data arriving in the output register. The memory manufacturer lists the best possible setting as the CL rating.
Command Rate CMD (1 / 2)
(Command Rate, MA 1T/2T Select) Number of clock cycles needed to address the memory module and the memory chip with the desired data zone. If your memory banks are full to capacity, you will have to raise this rate to two, resulting in a considerable drop in performance.
RAS Precharge Time TRP (2 / 3)
(RAS Precharge, Precharge to active) Number of clock cycles needed to precharge the circuits so that the row address can be determined.
RAS-to-CAS Delay TRCD (2 / 3/ 4/ 5)
(RAS to CAS Delay, Active to CMD) Number of clock cycles that pass between the row address being determined and the column address being sent out. Setting this value to two clock cycles can enhance performance by up to four percent.
Row Active Time TRAS (5 / 6/ 7)
(Active to Precharge Delay, Precharge Wait State, Row Active Delay, Row Precharge Delay) Delay that results when two different rows in a memory chip are addressed one after another.
Memory Clock (100/ 133/ 166/ 200 MHz)
(DRAM Clock) Specifies the clock speed of the memory bus. This rate is normally specified relative to the front-side bus clock. DDR technology (double-data rate) doubles the data rate given by the actual bus clock speed.