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AMD Shows New 3D V-Cache Ryzen Chiplets, up to 192MB of L3 Cache, 15% Gaming Improvement (Updated)

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(Image credit: AMD)

Update 6/1/2021 10am PT: AMD has confirmed to Tom's Hardware that Zen 3 Ryzen processors with 3D V-Cache will enter production later this year. The technology currently consists of a single layer of stacked L3 cache, but the underlying tech supports stacking multiple dies. The technology also doesn't require any specific software optimizations and should be transparent in terms of latency and thermals (no significant overhead in either). We also obtained further fine-grained details, stay tuned for additional coverage.

Original Article: 

AMD just changed the game entirely. AMD made a stunning disclosure at Computex 2021 — the company has 3D-stacked chiplets based on the Zen 3 architecture that will go into production this year. These innovative new chiplets feature an additional 64MB of 7nm SRAM cache (called 3D V-Cache) stacked vertically atop the core complex die (CCD) to triple the amount of L3 cache for the CPU cores. That technique can yield up to an amazing 192MB of L3 cache per Ryzen chip — a massive improvement over the current limit of 64MB.

AMD CEO Lisa Su also showed a prototype Ryzen 9 5900X chip that the company already has up and running and provided a pretty impressive demo of accelerated gameplay due to the new architecture — the gains in 1080p gaming averaged in the 15% range. That's the type of gains that we typically associate with a new CPU microarchitecture and/or process node, but AMD accomplished this feat with the same 7nm node and Zen 3 architecture that already ships with its standard Ryzen 5000 models.  

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3D V-Cache

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3D V-Cache

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3D V-Cache

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AMD bonds the 3D cache to the top of the Ryzen CCD with TSVs (through silicon vias) that enable up to 2 TB/s of bandwidth between the chip and the cache. This technique comes courtesy of TSMC's 3DFabric technology, which we covered here. Here's an animation (expand the tweet below):

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AMD also thins the 3D cache die and adds structural silicon to the chip, resulting in a final Ryzen processor that looks identical to a regular chip. 

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(Image credit: AMD)

Su showed a prototype Ryzen 9 5900X with the 3D chiplet technology already infused. You can see the 6 x 6mm hybrid SRAM bonded to the top of the chiplet (left chiplet in the image above). Finished devices will have 96MB of cache per CCD, for a total of an almost insane 192MB of L3 cache for a 12- or 16-core Ryzen 5000 processor. 

3D V-Cache

(Image credit: AMD)

AMD used a hybrid bond approach with TSVs that provides over 200X the interconnect density of 2D chiplets, a 15X improvement in interconnect density over micro-bump 3D implementations, and a 3X improvement in interconnect energy efficiency.

Su said these incredible advances come courtesy of a microbump-less die-to-die interface that uses a direct copper-to-copper bond to improve thermals, density, and interconnect pitch, along with yielding incredible energy advances. Su said this combination of attributes makes this approach the most advanced and flexible active-on-active silicon stacking tech in the world. 

3D V-Cache

(Image credit: AMD)

Su demoed the Ryzen 9 5900X prototype with the new 3D V-Cache against a standard 5900X, with both chips locked at a 4.0 GHz clock speed. The 3D prototype provided a 12% increase in the triple-A title Gears 5. 

3D V-Cache

(Image credit: AMD)

To drive the point home, Su showed a broader selection of game benchmarks that show the Ryzen 9 5900X with 3D V-Cache technology providing an average of 15% more performance across a broad spate of games at 1080p. That includes titles like Dota 2, Monster Hunter World, League of Legends, and Fortnite.

We have a million questions, such as if the cache has a higher latency than the 'normal' L3 cache, which might require software optimizations to accommodate. We'll be busy following up with AMD for more detail, and better images. 

Su said that the company will be ready to start production with its "highest-end products" with 3D chiplets at the end of the year. This is just the first implementation of the stacking tech — AMD can use it for other functions in the future, too. The implications of that on both the client and the enterprise side are quite profound, so we'll be following up for more detail. Stay tuned. 

  • Dragonwatcher
    Next step a terminator type 3-dimensional CPU. Followed very closely by skynet v1.0. But other than that frikken AWESOME. Wonder what it is going to slot into AM4 or AM5.
    Reply
  • dehjomz
    Did this just make Alder Lake-S irrelevant? I was rooting for Intel, but I don’t know how they’re gonna compete with this…
    Reply
  • turbomode99
    Cache has diminishing returns after a certain point and also with larger cache sizes, latency tends to increase. We'll see how it ends up performing.
    Reply
  • CerianK
    Dragonwatcher said:
    Wonder what it is going to slot into AM4 or AM5.
    It was shown on 5900X and directly compared, so likely both AM4 and AM5 moving forward (unless AM5 is segmented away from it, e.g. only TR and Epyc).
    Reply
  • jasonkaler
    turbomode99 said:
    Cache has diminishing returns after a certain point and also with larger cache sizes, latency tends to increase. We'll see how it ends up performing.
    Every time you double the size of the cache you increase its performance by 50%
    Reply
  • dave.jeffers
    dehjomz said:
    Did this just make Alder Lake-S irrelevant? I was rooting for Intel, but I don’t know how they’re gonna compete with this…
    ummm, I think so!
    Reply
  • Kamen Rider Blade
    Is there any other material they could place inside parts of the Structural Silicon to help transfer heat away from the die?
    Reply
  • hotaru251
    Kamen Rider Blade said:
    Is there any other material they could place inside parts of the Structural Silicon to help transfer heat away from the die?
    not really.

    There are testing being done with actual nano sized watercooling built into dies but still not an actual thing that might come to market.
    Reply
  • nitrium
    Intel might actually be forced to innovate for a change. The last time that happened was when AMD released the Athlon 64 series of CPUs back in 2004/2005.
    Reply
  • hotaru.hino
    nitrium said:
    Intel might actually be forced to innovate for a change. The last time that happened was when AMD released the Athlon 64 series of CPUs back in 2004/2005.
    Intel has been innovating. The problem is they don't have anything to show for it because of the woes trying to get off 14nm.
    Reply