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Intel Alder Lake PCIe 5.0 Configuration Reportedly Detailed In Coreboot
Alder Lake won't just be the first to bring an x86 hybrid architecture to desktops; the processors have also been pegged to leverage the high-velocity PCIe 5.0 interface. Coreboot (via Komachi_Ensaka), an open-source substitute for UEFI, seems to contain valuable information on the potential PCIe configuration that we could see on Alder Lake.
Early rumors claimed that the 12th Generation Alder Lake processors would support both the PCIe 5.0 and PCIe 4.0 standard, and Tim Wawrzynczak's assessment of the code seems to confirm that. However, the code specifically references Alder Lake-P (ADL-P), so it's uncertain if the same setup will translate over to the Alder Lake-S lineup. We still have no idea what Alder Lake-P will be, but some think it could be Intel's Atom P-series or a mobile chip. In any event, a previous coreboot patch revealed that Alder Lake-P could max out at 14 cores, six Golden Cove cores, and eight Gracemont cores.
Alder Lake-P appears to provide a flexible PCIe layout. The processor reportedly offers one PCIe 5.0 x8 lane or two PCIe 4.0 x4 lanes. The PCIe 5.0 lane has no problem running at x4. It would appear that neither interface supports bifurcation, meaning you can't split up the PCIe 5.0 lane or get the PCIe 4.0 lanes to operate at x8. Nonetheless, both are backward compatible with previous-gen devices.
Swipe to scroll horizontally
Interface
x16
x8
x4
x2
x1
PCIe 5.0
64 GBps
32 GBps
16 GBps
8 GBps
4 GBps
PCIe 4.0
32 GBps
16 GBps
8 GBps
4 GBps
2 GBps
PCIe 3.0
16 GBps
8 GBps
4 GBps
2 GBps
1 GBps
PCIe 2.0
8 GBps
4 GBps
2 GBps
1 GBps
0.5 GBps
PCIe 1.0
4 GBps
2 GBps
1 GBps
0.5 GBps
0.25 GBps
A single PCIe 5.0 x8 lane might sound lackluster at first, but it actually provides plenty of bandwidth. PCIe 5.0 x8 is essentially equivalent to PCIe 4.0 x16; therefore, the interface is good for up to 32 GBps of bandwidth, which is more than any consumer PCIe-based device can consume.
Only AMD's Ryzen 3000 and Ryzen 5000 mainstream processors have embraced the PCIe 4.0 standard on a desktop platform at this point. Intel's imminent Rocket Lake should change that panorama.
There are quite a few mainstream PCIe 4.0 products, including graphics cards and M.2 SSDs, on the market right now. Tests have shown that even the fastest graphics cards have yet to saturate a PCIe 3.0 x16 interface, much less PCIe 4.0. M.2 SSDs, on the other hand, have been able to exploit the extra bandwidth that PCIe 4.0 brings to the table. We expect the PCIe 5.0 situation to play out the same.
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Zhiye Liu is a news editor, memory reviewer, and SSD tester at Tom’s Hardware. Although he loves everything that’s hardware, he has a soft spot for CPUs, GPUs, and RAM.
"We expect the PCIe 5.0 situation to play out the same."
PCIE5 doubles the max bandwidth per lane, so perhaps a single lane would do for a PCIE5 SSD and perhaps 3 lanes would do for a GPU.
I suspect Intel wants to use the PCIE5 to show off CXL performance increases for GPUs, since that is what they have announced with the Sapphire Rapids Server chips.
"It would appear that neither interface supports bifurcation, meaning you can't split up the PCIe 5.0 lane or get the PCIe 4.0 lanes to operate at x8."
PCIE5 is backwards compatible with all prior pcie versions. It starts negotiations at PCIE1.
The patch comments also explicitly say that the 8 lanes of PCIE5 can be split into two groups of 4 lanes.
the interface is good for up to 32 GBps of bandwidth, which is more than any consumer PCIe-based device can consume.
I could imagine a low-end GPU needing to use system RAM to supplement its 4-6GB of VRAM using a good chunk of that 32GB/s. That's where the 4GB RX5500 gets its huge 4.0x8 vs 3.0x8 boost (closes 70-80% of the gaps with the 8GB variant) from. I count that as at least one thing in consumer space that could significantly benefit from it as soon as lower-end 5.0x8 GPUs become available.
Would be great if my 6 year old PC holds out until PCI-e 5.0 appears on intel motherboards. Maybe by then, they'll have a GPU available that is actually noticeably hindered by PCI-e 3.0. From what I've seen, even with the RTX 3090, there's literally only a couple of FPS difference in performance between PCI-e 3.0 and PCI-e 4.0.
From what I've seen, even with the RTX 3090, there's literally only a couple of FPS difference in performance between PCI-e 3.0 and PCI-e 4.0.
With the 4GB RX5500, 4.0x8 vs 3.0x8 can make the difference between 40fps and 70fps whereas the 8GB variants score 80fps regardless, almost making the 8GB models unnecessary. Had the RX5500 had a 4.0x16 interface, the 8GB models' VRAM size advantage would have been mostly irrelevant.
People keep gawking over the high-end but it is the lower-end GPUs that would benefit the most from 5.0x16 on a DDR5 platform once the parts become affordable.
Surely my new Capellix AIO footprint will not cover or adequately cool the new much larger upcoming LGA 1700.
The only area of the IHS that really needs to make contact with the HSF or cooling block is the area surrounding the cores and that area is only a small fraction of the total IHS surface. As long as your AiO's manufacturer makes an updated bracket to locate the block over the correct spot, you'll be fine.
At CES 2021, Intel gave a sneak peek at a desktop PC running Windows on an Alder Lake chip ... They also said these are coming in 2H 2021. The slide in that presentation indicated Alder Lake versions will exist for both mobile and desktop, which confirms rumors.
