SK Hynix Reveals 238-Layer 3D NAND: Cheap and Fast SSDs Incoming

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SK Hynix increases number of 3D NAND layers to 238.

SK Hynix has introduced its first 3D NAND device featuring 238 layers, the highest number of layers in the industry. The new 512Gb devices promise to be rather cheap and will enable SK Hynix to build inexpensive solid-state storage. Also, 512Gb 238-layer 3D NAND products will help the memory maker learn how to mass produce flash memory with a high number of layers.  

SK Hynix's first 3D NAND device with 238 layers features a triple level cell (TLC) architecture, a capacity of 512Gb (64GB) as well as a 2400 MT/s interface speed, a 50% increase compared to previous-generation flagship NAND from the South Korean manufacturer. As an added bonus, the new 3D NAND memory device reduces power consumption during reads by 21%, which will be an advantage for mobile PCs as well as smartphones. 

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Anton Shilov
Anton Shilov
Contributing Writer

Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.

3 Comments Comment from the forums
  • bit_user
    I think the article says "1 Gb" in several places where it ought to say "1 Tb".
    Reply
  • MeeLee
    "4D NAND"???
    Let's not get ahead of ourselves, just because someone does 238 layers of what initially started as SLC, and evolved to DLC, TLC and now MLC.
    MLC nand, be it 3D or regular, can have a very large amount of layers. To become 4D nand, it'd have to shape shift in our realm, and I don't see that happening anytime soon.
    Reply
  • bit_user
    MeeLee said:
    "4D NAND"???
    Let's not get ahead of ourselves, just because someone does 238 layers of what initially started as SLC, and evolved to DLC, TLC and now MLC.
    MLC nand, be it 3D or regular, can have a very large amount of layers. To become 4D nand, it'd have to shape shift in our realm, and I don't see that happening anytime soon.
    I sympathize with your sentiment, but just want to point out that I think the PUC is how they justify calling it "4D". Not that it makes much more sense, but I guess the idea is they're not only stacking layers of NAND, but also putting the controller underneath it all. So, that extra degree of stacking somehow qualifies it as "4D".

    Or, maybe it's intended to refer to the fact that they're packing multiple bits per cell. So, to address a bit, you'd need to specify the: plane, x coordinate, y coordinate, and which bit in the cell. However, I think it's not their first 3D TLC or at least MLC chip, so it's a little hard to see why it would suddenly now qualify as 4D.

    Another way you can justify calling something "4D" is if the interconnect topology warrants it. But nothing about that is mentioned.
    Reply