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ZeroPoint Technology AB Secures $2.5 Million for Hardware Based RAM Data Compression

Steam Deck Hardware Analysis
(Image credit: Shutterstock)

ZeroPoint Technologies AB, a Swedish startup company appearing as a spinout of the Chalmers University of Technology, has today announced its latest work. Ziptilion, a memory technology that has been awarded a patent, €2.5 million (just under $3 million) in seed funding, and promises to double your RAM capacity and bandwidth, all while achieving higher power efficiency.

Many of you remember the old RAM doubling software that existed back in the 80s and 90s. They were a big scam at the time, promising users who purchased the software double their ram capacities without a proper hardware upgrade. Today, ZeroPoint plans to do that, however, with a completely different, hardware-based approach.

Called the Ziptilion, this hardware IP works by compressing memory data using proprietary compression algorithms, and ZeroPoint claims an2-3 times increase in bandwidth. The way Ziptilion works is by embedding the IP into a design, and it works directly with a memory controller and processor's cache subsystem, using the industry-standard SoC AXI interconnect fabric. The company claims that its technology can compress memory in such an efficient way that memory latency mostly is reduced by using the Ziptilion IP, as it fetches the compressed data from and to the memory. In extreme cases, the latency can be higher approximately 1-100 nanoseconds, however, the gains are outweighing the downsides. 

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ZeroPoint Ziptilion IP

(Image credit: ZeroPoint Ziptilion IP Whitepaper)
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ZeroPoint Ziptilion IP

(Image credit: ZeroPoint Ziptilion IP Whitepaper)

And you might wonder what is the cost of this IP? Well, according to the company, there exists a design on TSMC's 28nm node that implemented the Ziptilion IP on the AXI bus running at 800 MHz frequency and with a bandwidth of 32 GB/s. The average 7 nm dual-channel memory design that uses this IP will gain only 1.36 square millimeters of extra die usage, while a server CPU with an eight-channel memory controller will require additional 3.02 square millimeters for embedding it.

(Image credit: ZeroPoint Ziptilion IP Whitepaper)

In terms of performance, the Ziptilion IP whitepaper has compared its compression technology with the addition of more RAM. Precisely, the whitepaper compared the impact of doubling the system's RAM capacity with an addition of Ziptilion design to the SoC. It concludes that the new technology can bring very similar results, effectively doubling your working ram capacity thanks to the compressed data.

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ZeroPoint Ziptilion IP

(Image credit: ZeroPoint Ziptilion IP Whitepaper)
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ZeroPoint Ziptilion IP

(Image credit: ZeroPoint Ziptilion IP Whitepaper)

And for possible applications, the design can be implemented in many forms. More specifically, a SoC like the one found on Raspberry Pi and the smartphone SoCs can benefit greatly from it, as those systems are limited by the system memory they are equipped with. A simple smartphone with 8 GB of RAM could see a boost up to 16 GB RAM with this IP block, as an example.

While we don't know if this technology will ever make it to the mainstream market, it does show promise, unlike the RAM doublers of yesteryear. The people behind the technology have been researching memory compression algorithms for over 15 years, and it looks like the market is finally ready for something like this to be embedded into future designs.