- A Look At AMD's Socket AM2 Platform
- Will Core Duo Notebooks Trade Battery Life For Quicker Response?
- AMD Athlon FX-60's Dual-Core Assault
- The 65 nm Pentium D 900's Coming Out Party
- Intel's 65 nm Process Breathes Fire into Double-Core Extreme Edition
- Top Secret Intel Processor Plans Uncovered
- Are Three Cores Better Than Two?
- The Mother of All CPU Charts 2005/2006
- Single-Core CPUs Ain't Dead Yet
- Virtual Infrastructure Summit At VMWorld 2005
Advanced Smart Cache
Source: Tom's Hardware US – Keywords: idf, spring, 2006
Syndication:
Advanced Smart Cache

The unified L2 cache probably is the feature that is mentioned first. It allows for a large L2 cache to be shared by two processing cores (2 MB or 4 MB). Caching can be more effective because data is no longer stored twice into different L2 caches any more (no replication). The full L2 cache is highly dynamic and can adapt to each core's load, which means that one single core may allocate 100% of the L2 cache area dynamically if this is required (on a line by line basis).
Sharing data also is more efficient now, because no front side bus load is generated while reading or writing into the cache (which is the case with the Pentium D), and there is no stalling when both cores are trying to access it. A good example that shows the advantages in multi-threaded environments is one core writing data into the cache, while the other may read something else at the same time. Cache misses are reduced, latency goes down, and access by itself also is faster now, because the Front Side Bus definitely was a limiting factor.
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