The unified L2 cache probably is the feature that is mentioned first. It allows for a large L2 cache to be shared by two processing cores (2 MB or 4 MB). Caching can be more effective because data is no longer stored twice into different L2 caches any more (no replication). The full L2 cache is highly dynamic and can adapt to each core's load, which means that one single core may allocate 100% of the L2 cache area dynamically if this is required (on a line by line basis).
Sharing data also is more efficient now, because no front side bus load is generated while reading or writing into the cache (which is the case with the Pentium D), and there is no stalling when both cores are trying to access it. A good example that shows the advantages in multi-threaded environments is one core writing data into the cache, while the other may read something else at the same time. Cache misses are reduced, latency goes down, and access by itself also is faster now, because the Front Side Bus definitely was a limiting factor.
- IDF Spring 2006: The Core Of Intel 3.0
- Intel's Energy Awakening
- Quad Cores In Multi-Chip Packages By 2007
- Core To The Rescue
- Wide Dynamic Execution
- Advanced Digital Media Boost
- Advanced Smart Cache
- Smart Memory Access
- Memory Disambiguation
- Intelligent Power Capability
- The Memory Controller Question
- There Is More To Save
- The Server Challenge
- Mashups To Drive Mobility
- Robson NAND Flash Or Hybrid Hard Drives?