IDF Spring 2006: Will Intel's Core Architecture Close the Technology Gap?

Wide Dynamic Execution

In addition to that, the Core architecture supports the techniques that the Pentium M applies to reduce the total number of micro-ops: Micro Ops are broken down x86 instructions that the processor understands. Two of these can be fused into another micro op in order to save time (and energy). According to Intel, roughly every 10th instruction can be merged with another one using Micro Ops Fusion.

The idea of fusing micro ops has also been applied to the instruction level (instruction level parallelism) by allowing for two independent instructions (e.g. a compare and a jump) to be merged for decoding and execution. This feature, which is called Macro Ops Fusion, can even be carried into the ALUs: These allow for overall single cycle instruction execution, whether that is a macro op that consists of two instructions or generic instructions.

Both fusion mechanisms together can help to increase the efficiency of each core considerably. Think about it as some sort of instruction or micro ops level.

TOPICS
Patrick Schmid
Editor-in-Chief (2005-2006)

Patrick Schmid was the editor-in-chief for Tom's Hardware from 2005 to 2006. He wrote numerous articles on a wide range of hardware topics, including storage, CPUs, and system builds.