All of Intel's Tiger Lake CPUs may not be out yet, but Intel apparently has pre-release mobile Alder Lake CPUs already in the wild. A 14 core mobile Alder Lake chip was spotted in Geekbench 5 flexing its iGP in the OpenCL benchmark.
If you're unfamiliar with Alder Lake, the architecture will be Intel's successor to the upcoming 11th Gen Rocket Lake and Tiger Lake (desktop/mobile) architectures. What makes Alder Lake so interesting is its radical new design in implementing a hybrid core architecture involving smaller "power-saver" cores and larger performance cores. The strategy is similar to ARMs big.LITTLE architecture found in Apple, Samsung, and Qualcomm ARM-based processors, which also utilize performance cores and power-saver cores.
This is why Geekbench 5 shows the Alder Lake chip as having an unusual 14 core/20 thread configuration. We believe the power-saver cores lack hyperthreading, so that would indicate the Alder Lake chip has a standard hexa-core design for the performance cores, then eight additional power saver cores.
Unfortunately, we don't get a clue as to how the cores will behave in Geekbench, but we do get an idea of how its Intel Xe IGP may perform. The chip's Xe graphics scored 13438 points in Geebench 5's OpenCL test. For comparison, that's around GTX 660 Ti performance, or for a more modern comparison, comparable to AMD's Vega 11 graphics found in processors like the 3400G.
The score is pretty underwhelming, as current Xe integrated graphics chips are capable of overpowering AMD's Vega iGPs quite easily. But this is a prototype, so things are bound to change. Plus, Geekbench 5 isn't exactly a great benchmark for real-world performance.
Either way, it's cool to see a mobile Alder Lake chip in action. This architecture is a radical change from anything Intel has produced over the past decade. It'll be very interesting to see how much power-saver cores will benefit traditional desktops and laptops in the near future.
And that is completely aside to how I do not have any idea whatsoever why a high performance desktop user would want die space wasted on throwing weak "power saving" cores in the mix, probably messing up Window's scheduler. This is an idea they had to try and add a good thread or two into their extreme-low-end Atom processors, which at makes some sense. Absolutely terrible idea to essentially cut out a chunk of their desktop processor and replace it with cores that Google doesn't even want in their Chromebooks.
But on Mobile Side, I can see the value proposition for "little" atom cores to save on power.
But that's a side effect of just bad power consuming architecture & design & manufacturing process from the beginning to compete against AMD/TSMC.
Anyways, it's a interesting choice moving foreward.
I hope they get their Process/Thread scheduler implemented correctly on day one, or else they're going to catch alot of flak for it.
I for one, however, would like heterogenous cores in my processors. I'm not gaming 24/7 or doing some other task that requires high performance and it's kind of headscratching to me that my Ryzen 3700X needs as much power, if not more, running low-end tasks than what my laptop, which has a Ryzen 4900HS, takes in its entirety running those same tasks. And yet I see almost no practical performance benefit on my desktop.
If you need raw power, there's another market segment for you.
The Gracemont cores also have some instructions that support faster networking, similar to the Tremont cores. How Intel expects to take advantage of this in Alder Lake is a puzzle, as is the intended use of PCIE5 lanes.
Read the title..... it clearly says
Alder Lake Mobile CPU
WEll, thats precisely why this is a mobile CPU. Be it Intel or AMD, both are still nowhere near the power efficiency of ARM.
I want RISC-V to eat ARM's entire market little by little until ARM disappears or is left a husk of it's old self.
ISA has nothing to do with the power efficiency of a part. It's solely about the implementation of it in hardware. Case in point, one of the big reasons why Apple ditched PowerPC for x86 was because the manufacturers of PowerPC weren't making efficient enough parts.
Also on a side note, just because the ISA is open, doesn't mean the implementation is. Let's not delude ourselves into thinking that RISC-V is going to usher in some golden age of CPUs. It just makes it more convenient for other hardware manufacturers to roll out their own secret sauce.