Latest about EUV
SK hynix says its 3D DRAM is half as expensive to produce
SK hynix says adopting 4F2 structures and 3D transistors will increase the cost-efficiency of EUV lithography usage in DRAM production.
Samsung may start installing its first High-NA EUV litho tool in late 2024
Samsung will be about a year behind Intel in installing ASML's Twinscan EXE:5000 High-NA litho tool for development purposes.
Japanese scientists develop simplified EUV scanner that can make production of chips considerably cheaper
OIST's simplified EUV litho system uses two mirrors instead of six.
The U.S. has sanctioned 18 Chinese fabs, dozens remain in white zone
The U.S. government approves shipments of wafer fab equipment to many Chinese fabs, other are banned. Question is, can those tools be installed in banned fabs?
Tokyo Electron's new tool can reduce the necessity for EUV double patterning and improve yield
Tokyo Electron unveils the Acrevia tool, which can improve patterning with gas cluster beam technology.
Micron is the last memory maker to join the EUV party
Micron reiterates its plans to use EUV for high-volume DRAM production next year as it starts pilot production on a 1-gamma node.
Intel CEO says China must make its own chips if sanctions become too restrictive, points to EUV as key cutoff point
Intel CEO Pat Gelsinger told Tom's Hardware during a question and answer session at Computex 2024 that China must make its own processors if US sanctions on the latest chips become too restrictive.
ASML sets new chipmaking density record, proposes Hyper-NA tools
Smaller, faster transistors at unprecedented speed.
