Photonic latch memory could enable optical processor caches that run up to 60 GHz, twenty times faster than standard caches — optical SRAM stores and outputs data entirely as light, but density challenges remain

Researchers have built a prototype that paves the way for enabling light-powered processor caches that can run at up to 60 GHz in the future, or roughly 20 times faster than some modern processor caches. The functional regenerative "photonic memory latch," fabricated on the commercially available GlobalFoundries’ 300mm Fotonix photonics platform, is designed as an optical counterpart to a standard SRAM bit, and the team positions it as a missing component for fully photonic processors. However, further density improvements will be needed before the tech can be fully integrated into optical processors.

The prototype addresses two bottlenecks that plague modern high-performance systems — interconnect delay and the cost of repeatedly converting information between light and electricity.

Photonic accelerators and optical interposers can move data at extremely high speeds, but they still depend on electronic memory to store and refresh bits. That forces every data path to cross into the electrical domain before returning to light. In this research, the USC and UW engineers tackled that gap by building a memory system that stores, stabilizes, and outputs data entirely as light.

Their device uses a cross-coupled, differential architecture that parallels the behavior of an SRAM cell. The research team, led by Ajey Jacob at USC ISI and Akhilesh Jaiswal at UW-Madison, describes it as a latch that can be written optically and retain its state without drifting. Simulation studies exploring how the latch architecture could be scaled into a complete photonic SRAM system, with the latch acting as the optical equivalent of a single SRAM bit, have already been published by the authors.

The UW-Madison study describes the performance the team expects from the design, namely write speeds approaching 20 GHz, while modeled read speeds reach 50-60 GHz. Those figures sit well above the clock rates of electronic SRAMs used in today’s CPUs and accelerators, which usually top out at 2-3 GHz.

These higher speeds come with footprint trade-offs, though, with photonic components remaining orders of magnitude larger than nanoscale CMOS transistors; this massively limits density. Instead, the researchers point to applications where size is less of a restrictive factor, such as high-bandwidth links inside data centers and HPC systems.

The decision to fabricate the latch on GlobalFoundries’ Fotonix platform means that the technology can be replicated and scaled more easily than if it relied on specialized materials or custom fabrication steps, as is often the case in optical memory research.

The researchers from the University of Southern California Information Sciences Institute and the University of Wisconsin-Madison presented their work at the International Electron Devices Meeting in San Francisco between December 6 and 10.

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