Industry's first TSMC COUPE-based optical connectivity solution for next-gen AI chips displayed — Alchip and Ayar Labs show future silicon photonics device

At TSMC's European OIP forum this week, Alchip and Ayar Labs demonstrated a fully integrated, in-package optical I/O engine built on TSMC's COUPE platform that enables optical connectivity for next-generation AI accelerators. The solution — which combines Ayar's silicon-photonics TeraPHY IC with Alchip's electrical interface die and a detachable fiber connector — can deliver up to 100 Tb/s of bandwidth per accelerator and connect to other chips using the industry-standard UCIe interface. The solution is aimed at hardware developers who need optical connectivity but cannot build their own optical subsystem from scratch.

When TSMC introduced its Compact Universal Photonic Engine (COUPE) framework in 2024, the company primarily targeted large chip developers like AMD or Nvidia that can afford to build their own electronic integrated circuits (EICs) and photonic integrated circuits (PICs), and then order TSMC to build them.

However, many designers of custom accelerators do not have resources for vertical integration (unlike Nvidia, which controls the whole stack of technologies — from compute to scale-out connectivity — with its NVL72, NVL144, and NVL576 platforms) tend to license everything they can and then focus on developing IPs that differentiate their solution from others. This is where the production-ready optical subsystem from Alchip and Ayar Labs comes into play, enabling smaller chip designers to add optical connectivity to their chips relatively easily without investing tens of millions of dollars upfront.

The solution jointly developed by Alchip and Ayar Labs is a three-chiplet co-packaged optical I/O subsystem that consists of an Alchip UCIe-A to UCIe-S protocol-converter chiplet that terminates the accelerator's UCIe-A interface and implements scale-up protocols (UALink, PCIe, Ethernet, SUE) over UCIe-S (streaming), an Alchip EIC that provides low-power SerDes, modulation drivers, clocking, and control, and an Ayar Labs TeraPHY PIC that performs the optical modulation and detection using silicon photonics.

The Alchip protocol converter can also carry non-UCIe protocols encapsulated over the UCIe physical interface, so it can work with compute dies that use proprietary protocols. The PIC uses a microring architecture and is delivered with detachable fiber connectors for manufacturability and offers two link options: PAM4 CWDM (100–200 ns per hop, BER < 10⁻⁶) and a DWDM fast-follower (20–30 ns per hop, BER < 10⁻¹²).

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The optical subsystem can achieve extreme scale-up, supporting 100+ Tb/s of bandwidth per accelerator and 256+ optical ports per device to connect hundreds of processors across multiple racks and operate them as a single large processor. Alternatively, the companies envision that their solution could be used for memory extenders as well.

The reference design (a mockup) includes two full-reticle accelerator dies, eight HBM stacks, four protocol-converter chiplets, and eight Ayar Labs TeraPHY optical engines, all mounted on a single substrate with integrated passive devices for power integrity. Alchip's system diagrams demonstrate the platform connecting XPU-to-XPU, XPU-to-switch, and switch-to-switch, and even enabling optical memory expansion.

By using the subsystem from Alchip, which will be sold in the form of chiplets, almost any developer of AI accelerators can enable ultra-high-bandwidth, low-latency, and energy-efficient rack-scale and even multi-rack-scale connectivity for their accelerators, which is too costly to develop in-house for a small company.

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