6.4 GB/s Memory Bandwidth: Infrastructure For The Future
While testing, we were quickly able to determine that the 875P chipset has a very high performance. It was clear to us that this is not due to the dual-channel operation for DDR400 alone. Intel must have invested considerable development efforts in the MCH memory interface. The crux of the matter lies in the hardware's Performance Acceleration Technology (PAT), as the marketing strategists have dubbed it.
Does the inexpensive Springdale chipset have it, too? Unfortunately, no...
Intel uses a small trick in order to squeeze an extra drop out of the MCH. Through an improvement in the logic design, the manufacturer has succeeded in saving one cycle when the CPU requests to perform a memory access, and a further cycle with the DRAM Chip Select. However, this only works with the 875/ Canterwood and 200 MHz FSB. The Springdale does not have PAT. Generally, the selection process for the Canterwood and Springdale chipsets is made based on "Speed Binning," as it is already known in the fabrication process of CPUs. If the silicon does not meet the requirements of the Canterwood qualification, such as PAT, then it can only be put through the Springdale qualification test. The chip makes a trip to the garbage bin only when it fails both of the tests.
By the way, with regard to the two cycles spared - clever Intel strategists give them impressive-sounding names, such as "bypass paths" and "faster paths" even though they only reduce the latency time of the memory.
For the tech-savvy: That's the way how Intel achieves an performance jump through PAT
